AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 5

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

TABLE OF CONTENTS
Distinctive Characteristics ......................................................................................................................................... 1
General Description .................................................................................................................................................. 1
Block Diagram........................................................................................................................................................... 2
Logic Symbol ........................................................................................................................................................... 3
Ordering Information ................................................................................................................................................. 4
Connection Diagrams and Pin Designations ............................................................................................................ 8
Pin Description ....................................................................................................................................................... 12
Functional Description ........................................................................................................................................... 17
Clock Control ......................................................................................................................................................... 34
SRESET Function .................................................................................................................................................. 38
System Management Mode ................................................................................................................................... 38
Test Registers 4 and 5 Modifications ..................................................................................................................... 51
Am486 Microprocessor Functional Differences ..................................................................................................... 54
Enhanced Am486DX CPU Identification ................................................................................................................ 55
Electrical Data ........................................................................................................................................................ 56
Absolute Maximum Ratings .................................................................................................................................... 57
Operating Ranges ................................................................................................................................................... 57
DC Characteristics Over Commercial and Industrial Operating Ranges ................................................................ 57
Switching Characteristics Over Commercial and Industrial Operating Ranges ...................................................... 58
AC Characteristics for Boundary Scan Test Signals at 25 MHz ............................................................................. 59
Switching Waveforms ............................................................................................................................................. 60
Package Thermal Specifications ............................................................................................................................ 64
Physical Dimensions .............................................................................................................................................. 65
168-Pin PGA (Pin Grid Array) Package ............................................................................................................. 8
168-Pin PGA Designations (Functional Grouping) ............................................................................................ 9
208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................................... 10
208-Pin SQFP Designations (Functional Grouping) ........................................................................................ 11
Overview .......................................................................................................................................................... 17
Memory ............................................................................................................................................................ 17
Modes of Operation ......................................................................................................................................... 17
Cache Architecture .......................................................................................................................................... 17
Write-Back Cache Protocol ............................................................................................................................. 18
Cache Replacement Description ..................................................................................................................... 19
Memory Configuration ..................................................................................................................................... 19
Cache Functionality in Write-Back Mode ......................................................................................................... 19
Cache Invalidation and Flushing in Write-Back Mode ..................................................................................... 31
Burst Write ....................................................................................................................................................... 32
Clock Generation ............................................................................................................................................. 34
Stop Clock ....................................................................................................................................................... 34
Stop Grant Bus Cycle ...................................................................................................................................... 35
Pin State During Stop Grant ............................................................................................................................ 35
Clock Control State Diagram ........................................................................................................................... 36
Overview .......................................................................................................................................................... 38
Terminology ..................................................................................................................................................... 38
System Management Interrupt Processing ..................................................................................................... 39
Entering System Management Mode .............................................................................................................. 43
Exiting System Management Mode ................................................................................................................. 43
Processor Environment ................................................................................................................................... 43
Executing System Management Mode Handler .............................................................................................. 44
SMM System Design Considerations .............................................................................................................. 47
SMM Software Considerations ........................................................................................................................ 51
TR4 Definition................................................................................................................................................... 52
TR5 Definition................................................................................................................................................... 53
Using TR4 and TR5 for Cache Testing ............................................................................................................ 53
DX Register at RESET .................................................................................................................................... 55
CPUID Instruction ............................................................................................................................................ 55
Power and Grounding ...................................................................................................................................... 56
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
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