AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 29

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

Step 9 One cycle after BOFF is deasserted, the cache
Step 10 The write-back access is finished when BLAST
Step 11 The BIU restarts the aborted cache line fill with
Step 12 In the same clock cycle, the snooping cache
Step 13 The previous read is now reread.
3.8.7 Special Scenarios for AHOLD Snooping
In addition to the previously described scenarios, there
are special scenarios regarding the time of the EADS
and AHOLD assertion. The final result depends on the
time EADS and AHOLD are asserted relative to other
processor-initiated operations.
3.8.7.1
Scenario : The MESI cache protocol and the ability to
perform and respond to snoop cycles guarantee that
writes to the cache are logically equivalent to writes to
memory. In particular, the order of read and write oper-
ations on cached data is the same as if the operations
Note:
The circled numbers in this figure represent the steps in section 4.8.6.
CLK
ADR
M/IO
CACHE
W/R
ADS
BLAST
BRDY
BOFF
AHOLD
INV
EADS
HITM
Data
immediately starts writing back the modified
line. This is indicated by ADS = 0 and W/R = 1.
and BRDY go active 0.
the previous read. This is indicated by ADS = 0
and W/R = 0.
drives HITM back to 1.
Write Cycle Reordering Due to Buffering
R1 from CPU
Figure 13. Cycle Reordering with BOFF (Write-Back)
W1 to CPU
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
don’t care
R1
R2
were on data in memory. Even non-cached memory
read and write requests usually occur on the external
bus in the same order that they were issued in the pro-
gram. For example, when a write miss is followed by a
read miss, the write data goes on the bus before the
read request is put on the bus. However, the posting of
writes in write buffers coupled with snooping cycles may
cause the order of writes seen on the external bus to
differ from the order they appear in the program. Con-
sider the following example, which is illustrated in Figure
14. For simplicity, snooping signals that behave in their
usual manner are not shown.
Step 1 AHOLD is asserted. No further processor-initi-
Step 2 The processor writes data A to the cache, re-
Step 3 The next write of the processor hits the cache
W1 from CPU
ated accesses to the external bus can be start-
ed. No other access is in progress.
sulting in a write miss. Therefore, the data is put
into the write buffers, assuming they are not full.
No external access can be started because
AHOLD is still 1.
and the line is non-shared. Therefore, data B is
written into the cache. The cache line transits
to the modified state.
W1
W2
W2
W3
W3
W4
W4
R2 from CPU
12
11
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