AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 23

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

3.8.3 External Bus Master Snooping Actions
The following scenarios describe the snooping actions
of an external bus master.
3.8.3.1
Scenario : A snoop of the on-chip cache does not hit a
line, as shown in Figure 6.
Step 1 The microprocessor is placed in Snooping
Step 2 EADS and INV are applied to the microproces-
Step 3 Two clock cycles after EADS is asserted, HITM
3.8.3.2
Scenario : The snoop of the on-chip cache hits a line,
and the line is not modified (see Figure 7).
Step 1 The microprocessor is placed in Snooping
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion. In the fastest case, this means that
HOLD was asserted one clock cycle before the
HLDA response.
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
becomes valid. Because the addressed line is
not in the snooping cache, HITM is 1.
mode with HOLD. HLDA must be High for a
minimum of one clock cycle before EADS as-
sertion.
HITM
CLK
ADR
INV
EADS
HOLD
HLDA
Note:
The circled numbers in this figure represent the steps in section 4.8.3.1.
Snoop Miss
Snoop Hit to a Non-Modified Line
Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
valid
valid
Step 2 EADS and INV are applied to the microproces-
Step 3 Two clock cycles after EADS is asserted, HITM
3.8.4 Write-Back Case
Scenario : Write-back accesses are always burst writes
with a length of four 32-bit words. For burst writes, the
burst always starts with the microprocessor line offset
at 0. HOLD must be deasserted before the write-back
can be performed (see Figure 8).
Step 1 HOLD places the microprocessor in Snooping
Step 2 EADS and INV are asserted. If INV is 0, snoop-
Step 3 Two clock cycles after EADS is asserted, HITM
In the fastest case, this means that HOLD was
asserted one clock cycle before the HLDA re-
sponse.
sor. If INV is 0, a read access caused the snoop-
ing cycle. If INV is 1, a write access caused the
snooping cycle.
becomes valid. In this case, HITM is 1.
mode. HLDA must be High for a minimum of
one clock cycle before EADS assertion. In the
fastest case, this means that HOLD asserts one
clock cycle before the HLDA response.
ing is caused by a read access. If INV is 1,
snooping is caused by a write access. EADS is
not sampled again until after the modified line
is written back to memory. It is detected again
as early as in Step 11.
becomes valid, and is 0 because the line is mod-
ified.
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