MC68HC811E2FN Freescale Semiconductor, MC68HC811E2FN Datasheet - Page 125
MC68HC811E2FN
Manufacturer Part Number
MC68HC811E2FN
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC811E2FN.pdf
(242 pages)
Specifications of MC68HC811E2FN
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
256Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Package Type
PLCC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Bit 5 — Unimplemented
MODF — Mode Fault Bit
Bits [3:0] — Unimplemented
8.7.3 Serial Peripheral Data I/O Register
The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register
initiates transmission or reception of a byte, and this only occurs in the master device. At the completion
of transferring a byte of data, the SPIF status bit is set in both the master and slave devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that
caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift
register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
Freescale Semiconductor
Always reads 0
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to
Select
Always read 0
0 = No mode fault
1 = Mode fault
and
Address:
8.6 SPI System
Reset:
Read:
Write:
$102A
Figure 8-5. Serial Peripheral Data I/O Register (SPDR)
Bit 7
Bit 7
Errors.
Bit 6
6
M68HC11E Family Data Sheet, Rev. 5.1
Bit 5
5
Indeterminate after reset
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
SPI Registers
8.5.4 Slave
125
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