PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 104

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
is terminated and a new interrupt is internally generated immediately after the access
has ended.
2.3.5
If the cannot continue the current operations in progress (e.g. due to a transient loss of
power) it stops operation and initializes all read/write registers to their reset state. After
that it sets the ABT bit of the STATUS register and generates an interrupt. The discards
all commands with the exception of a write command to the revision register while ABT
is set. Only after the write command to the revision register (with any value) the ABT bit
is reset and a reinitialization can take place.
2.3.6
The contains a revision register. This register is read only and does not influence
operation in any way. A write to the revision register clears the ABT bit of the STATUS
register but does not alter the content of the revision register.
2.3.7
The
registers: HWCONFIG0 to HWCONFIG3. These registers are usually only written once
during initialization and must not be changed while the is in active mode. It is mandatory
that the programmed configuration reflects the external hardware for proper operation.
Special care must be taken to avoid I/O conflicts or excess current by enabling inputs
without an external driving source. Table 80 can be used as a checklist.
Table 80
Register
HWCONFIG0
HWCONFIG0
HWCONFIG0
HWCONFIG1
HWCONFIG1
2.3.8
The locks itself to either an externally supplied frame sync signal or generates the frame
sync signal itself. This internal reference frame sync signal is called master frame sync
(MFSC). Table 81 shows how AFECLK and MFSC are derived by the . The bits ACT and
MFS are contained in the hardware configuration registers. The bit MFS controls
whether the frame sync is taken from external or generated internally. The bit ACT
enables the clock tracking and is explained in the sequel section.
can be adapted to various external hardware configurations by four special
Abort
Revision Register
Hardware Configuration
Hardware Configuration Checklist
Frame Synchronization
Name
PFRDY 1
OSC
ACS
MFS
ACT
1
Value
1
1
1
Check
FRDY must not float
OSC1/2 must be connected to a crystal
CLK must not float (tie low if no clock present)
FSC must not float (tie low if no clock present)
FSC must not float (tie low if no clock present)
104
PSB 4860
2000-01-14