PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 112

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However,
Figure 50 IOM
The supports both single clock mode and double clock mode. In single clock mode, the
bit rate is equal to the clock rate. Bits are shifted out with the rising edge of DCL and
sampled at the falling edge. In double clock mode, the clock runs at twice the bit rate.
Therefore for each bit there are two clock cycles. Bits are shifted out with the rising edge
of the first clock cycle and sampled with the falling edge of the second clock cycle. Figure
51 shows the timing for single clock mode and figure 52 shows the timing for double
clock mode.
Figure 51 IOM
DD/DR
DU/DX
FSC
DCL
DCL
FSC
programming is not supported via the monitor channels.
*
®
®
-2 Interface - Frame Start
-2 Interface - Single Clock Mode
bit 0
bit 0
T
T
1
1
112
bit 1
bit 1
T
T
2
2
bit 2
bit 2
PSB 4860
2000-01-14