PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 111

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.4
Interfaces
Interfaces
This section describes the interfaces of the . The supports both an IOM
single and double clock mode and a strobed serial data interface (SSDI). However, these
two interfaces cannot be used simultaneously as they share some pins. Both interfaces
are for data transfer only and cannot be used for programming the . The is slave and the
frame synchronization as well as the data clock are inputs. Table 87 lists the features of
the two alternative interfaces.
Table 87
Signals
Channels (bidirectional)
Code
Synchronization within frame by timeslot
2.4.1
The data stream is partitioned into packets called frames. Each frame is divided into a
programmable number of timeslots. Each timeslot is used to transfer 8 bits. Figure 49
shows a commonly used terminal mode (three channels ch
timeslots each). The first timeslot (in figure 49: B1) is denoted by number 0, the second
one (B2) by 1 and so on.
Figure 49 IOM
The signal FSC is used to indicate the start of a frame. Figure 50 shows as an example
two valid FSC-signals (FSC, FSC
clock cycle of a new frame (T
Data Sheet
DD/DU
FSC
Interfaces
SSDI vs. IOM
IOM
B1
®
®
-2 Interface
-2 Interface - Frame Structure
B2
ch
0
M0
®
-2 Interface
1
).
4
3
linear PCM (16 bit),
A-law, µ -law (8 bit)
(programmable)
CI0
*
) which both indicate the same clock cycle as the first
IC1
IOM
111
IC2
125 µ s
®
ch
-2
1
M1
CI1
6
1
linear PCM (16 bit)
by signal
(DXST, DRST)
0
, ch
1
ch
and ch
2
®
SSDI
-2 interface with
PSB 4860
2
2000-01-14
with four