PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 141

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3
The has a single status register (read only) and an array of data registers (read/write).
The purpose of the status register is to inform the external microcontroller of important
status changes of the and to provide a handshake mechanism for data register reading
or writing. If the generates an interrupt, the status register contains the reason of the
interrupt.
3.1
RDY
ABT
GAP
VOX
CIA
CIR
Data Sheet
RDY
15
ABT
Ready
0: The last command (if any) is still in progress.
1: The last command has been executed.
Abort
0: No exception during operation
1: An exception caused the to abort any operation currently in
Gap Being Detected
0: Currently no gap is being detected during recording
1: Currently a gap is being detected during recording
VOX detection
0: The input signal of the speech coder contains voice
1: The input signal represents silence, noise, constant or periodic signals
Caller ID Available
0: No new data for caller ID
1: New caller ID byte available
Caller ID Request
0: No new data for caller ID sender requested
1: New caller ID byte requested
Detailed Register Description
Status Register
GAP VOX
progress. The ABT bit is cleared by writing the revision register. No
other command is accepted by the while ABT is set.
CIR
CIA
CIS
CD
UTD
CPT
CNG
141
SD
ERR
BSY
DTV
ATV
DRQ
DA
PSB 4860
2000-01-14
PQE
PPI
0