PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 115

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.4.2
The SSDI interface is intended for seamless connection to low-cost burst mode
controllers (e.g. PMB 4725) and supports a single channel in each direction. The data
stream is partitioned into frames. Within each frame, one 16 bit value can be sent and
received by the . The start of a frame is indicated by the rising edge of FSC. Data is
always sampled at the falling edge of DCL and shifted out with the rising edge of DCL.
The SSDI transmitter and receiver are operating independently of each other except that
both use the same FSC and DCL signal.
2.4.2.1
The indicates outgoing data (on signal DX) by activating DXST for 16 clocks. The signal
DXST is activated with the same rising edge of DCL that is used to send the first bit (Bit
15) of the data. DXST is deactivated with the first rising edge of DCL after the last bit has
been transferred. The drives the signal DX only when DXST is activated. Figure 54
shows the timing for the transmitter.
Figure 54 SSDI Interface - Transmitter Timing
2.4.2.2
Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly
16 DCL clocks. As there may be more than one DRST pulses within a single frame the
can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In order to
detect the first pulse properly, DRST must not be active at the rising edge of FSC. In
figure 55 the is listening to the third DRST pulse (n=3).
Data Sheet
DU/DX
DXST
DCL
FSC
SSDI Interface
SSDI Interface - Transmitter
SSDI Interface - Receiver
bit 15
bit 14
125 µ s
bit 1
115
bit 0
PSB 4860
2000-01-14