RFW-D100 Vishay, RFW-D100 Datasheet
RFW-D100
Specifications of RFW-D100
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RFW-D100 Summary of contents
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... RFW-D100: Standard Interface to the RFW100 Series TABLE OF CONTENTS Description ...................................................................................................................................................................................... Features .......................................................................................................................................................................................... PIN Assignments ............................................................................................................................................................................ LQFP-44 - PIN FUNCTION............................................................................................................................................................. RFW-D100 Interface Description .................................................................................................................................................... Pin Descriptions .............................................................................................................................................................................. RFW-D100 Architecture .................................................................................................................................................................. RFW-D100 Description ................................................................................................................................................................... Oscillator Characteristics ................................................................................................................................................................ Reset............................................................................................................................................................................................... Power Saving Modes ...................................................................................................................................................................... Power Down Mode .......................................................................................................................................................................... Idle Mode ........................................................................................................................................................................................ PREAMBLE Correlation.................................................................................................................................................................. Refresh Bit ...................................................................................................................................................................................... Bit Structure .................................................................................................................................................................................... ...
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... In an RFWaves application, the MCU is in charge of the MAC layer protocol. The RFW-D100 was developed in order to reduce the real time demands of the MCU handling the MAC protocol. The RFW-D100 gives the MCU an easy parallel interface with the RFW122, similar to memory access. It converts the fast serial input to 8-bit words, which are much easier for an 8-bit MCU to work with ...
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... GND_IO 9 INT 10 VCC_IO 19278 Document Number 84675 For more information please contact: RFTransceivers@vishay.com Rev. 1.1, 22-Jan- RFWaves RFW-D100 YYWW0 Figure 1. The FRW-D100 - LQFP-44 RFW-D100 Vishay RFWaves RESERVED 32 GND_RF 31 VCC_RF 30 RF_ACTIVE 29 TX_RX 28 CMP_VREF 27 CMP_VIN 26 DATA_IO 25 RESERVED 24 VCC Core 23 GND Core 21 22 www.vishay.com 3 ...
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... DATA[0..7] SERIAL_IO ADDR[0..4] TX_RX RF ACTIVE RD_n WR_n CMP_VIN CS_n RESET POWER_DOWN IDLE_MODE CMP_VREF IDLE_RST INT WDT WDT_RST CLK RC_CAP SYSTEM_CLK OSC_I OSC_IO 6-24 MHz Figure 2. RFW-D100 Interface Description RFW122 DATA I/O RX_TX SHDWN CAP 19279 Document Number 84675 Rev. 1.1, 22-Jan-07 ...
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... SCR2(0) register. SCR3(7) and the capacitor discharge mechanism This output pin controls the RFW122 working/shutdown mode. Its 30 O This pin is the power supply input for the core logic of RFW-D100. A 0.1 µF power bypass capacitor should be placed between VCC 24 23 This pin is the ground for the core logic of RFW-D100. ...
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... Type 44 I/O This pin is the output of the inverting oscillator amplifier. This pin controls the power down mode of the RFW-D100. When this pin is set low, the clock generation in the oscillator block is disabled Going into power down and getting out of this mode will be discussed (X) in detail later on ...
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... Figure 3. Block Diagram of the RFW-D100 Internal Structure RFW-D100 DESCRIPTION Oscillator Characteristics The oscillator module can be used as the source of clock to the RFW-D100 stand alone module that can be bypassed. Optionally, an external oscillator can drive the RFW-D100, since the CLK1 pin is a primary clock input to the RFW-D100. When the oscillator ...
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... These modes enable the system to save power when the RFW-D100 is not in use. POWER DOWN MODE The MCU is able to halt all activity in the RFW-D100 by stopping its clock. This enables the MCU to reduce the power consumption of the RFW-D100 to a minimum. All registers and FIFOs retain their values when the RFW-D100 is in power-down mode ...
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... The value of the PREAMBLE is determined according to PRE-L and PRE-H registers for both the transmitter and the receiver. The value of the PRE-L and PRE-H registers should be identical in the RFW-D100 in all nodes in the same network. Document Number 84675 For more information please contact: RFTransceivers@vishay.com Rev ...
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... BLR=1. The number of clocks when the line is “1” is determined as follows: Number of “1”s = FLOOR* ((BLR + 6)/2). In case of “0” bit, RFW-D100 output “0” value for BLR + 6 clock pulses. * FLOOR - Rounds towards zero CRC The CRC is a redundant code, which is calculated and added to each packet on the transmitter side ...
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... The watchdog timer (WDT separate module inside the RFW-D100. A different oscillator from all the other modules in the RFW-D100 drives it. The watchdog clock source is an internal 10 kHz RC oscil- lator that uses an external capacitor to set its fre- Document Number 84675 For more information please contact: RFTransceivers@vishay ...
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... WDT pulse. 5. Enable WDT - SCR1(3) = ‘1’. The RX FIFO (FRC-L(0:7) + The purpose of having an input FIFO in the RFW-D100 is to reduce the real-time burden on the MCU. The FIFO is used as a buffer, which theoretically enables the MCU RX_FIFO_SIZE * 8 bit/byte * 1 µsec = 128 µsec, instead of every 1 µ ...
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... TX_AE. When SCR4(3) • TX_FIFO underflow flag (TX_UF in SSR) – If the RFW-D100 tries to read from an empty TX_FIFO, the RFW-D100 stops transmitting. The TX_EMPTY interrupt is invoked and TX_UF flag in SSR is set to ‘1’. TX_UF flag indicates the transmission has ended abnormally, since the RFW-D100 has tried to read from an empty TX_FIFO ...
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... Normal ending means that all the bytes of the packet including the CRC were transmitted. Abnormal ending means that either the RFW-D100 has been moved to RX mode in the middle of the packet by the MCU or the RFW-D100 www.vishay.com For more information please contact: RFTransceivers@vishay.com 14 has stopped transmitting since TX_FIFO has been empty when it should not have been ...
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... On the one hand, it has an internal comparator that gives it rough Radio Signal Strength Indicator (RSSI). The RSSI enables the RFW-D100 to identify any strong transmission that with good probability will block its transmission. On the other hand, it has an internal implementation of RFWaves Network Carrier Sense algorithm ...
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... MCU that the channel is free again. If the RFW-D100 identifies a packet, the carrier sense algorithm halts. When the RFW-D100 mode and LOCK flag in SSR is “0”, CS mechanism is working. When LOCK flag in SSR is “1”, CS mechanism is not working, since CS flag does not add any information because a PREAMBLE was identified, already ...
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... BIT LENGTH REGISTER (BLR) This register determines the length of the bit in terms of clock cycles. initiate a packet The bit length is (BLR + 6) clocks, since the RFW-D100 adds the value 6 to the value in BLR. The RFW-100’s bit rate is: Oscillator frequency/(BLR + 6). Default Value 6). Bit 5 Bit 4 Bit 3 ...
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... CRC 8 1 CRC 16 1 Bit 5: FIXED Controls the packet mode. When FIXED bit is high, the RFW-D100 sends and receives packets with a fixed size/length that is specified in the Packet Size Register (PSR). www.vishay.com For more information please contact: RFTransceivers@vishay.com 18 Whenever the counter reaches its overflow value (FRC-H(3-0), FRC-L), a pulse is generated in the WDT pin ...
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... There two cases in which SCR2(0) equals ‘0’ but TX_RX output pin mode (‘1’): SCR3(7) is set, then the RFW-D100 goes to RX mode and the output pin TX_RX goes to TX mode. 2. The capacitor discharge can change the output pin TX_RX to TX mode even if RFW-D100 are in RX mode ...
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... Bits 4-6: ZERO_DISCH_CNT [0:2] Determines the number of consecutive zero bits that will trigger a capacitor discharge by the zero counter capacitor discharge mechanism. ZERO DISCH CNT Bit 7: Not in Use This bit must all times for the RFW-D100 to work properly. Default Value PREAMBLE size ...
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... PREAMBLE). The location should be fixed for all the different kinds of packets transferred by NODE LOC 0 the network. 0 NET_ID location in the packet header must always be 1 before NODE_ID location RFW-D100 Vishay RFWaves BIt 2 Bit1 Bit 0 WIN CONT RF_ACTIVE IE Bit 2 Bit 1 Bit 0 ...
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... The CRC flag remains “1”, if the MCU does not read the SSR register. Bit 1: LOCKED_IN This flag indicates that a packet is being received. Bit 1 is set to logic 1 whenever the RFW-D100 identifies a new incoming packet (triggers LOCK_IN interrupt). After PREAMBLE, NET_ID, and NODE_ID have been identified, LOCKED_IN flag goes high. If NODE_ID and NET_ID are disabled, PREAMBLE identification is sufficient ...
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... TX_FIFO with the next packet. Bit 3: CS Carrier Sense detection bit. When this bit is high, the RFW-D100 has identified a structure of packet transmission in the air according to CSR. When low, no carrier has been detected. This bit is only valid in receive mode. The conditions for setting or clearing this flag are determined in the CS register ...
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... Bit 1: LOCK_OUT This bit reflects the LOCK_OUT flag interrupt when enabled by IER. LOCK_OUT interrupt is invoked whenever the RFW-D100 has finished receiving a packet. The end of the packet is determined according to the packet size. Bit 2: LINK_DIS This interrupt is invoked by the zero counter capacitor discharge mechanism. ...
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... SCR4 LCR BIR NIR PSR PPR BLR CSR IER --- IIR --- SSR --- TFR --- RFR --- Parameter Storage temperature range Supply voltage relative to GND Input voltage relative to GND Output voltage Analog pins Junction Operating RFW-D100 Vishay RFWaves Default Values --- --- --- --- --- ...
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... RFW-D100 Vishay RFWaves RECOMMENDED OPERATING CONDITIONS Symbol Parameter V Power supply CC V Input voltage IN T Operating temperature under bias OP GENERAL DC CHARACTERISTICS Symbol Parameter V Input low voltage IL (Schmitt trigger negative going threshold) V Input high voltage IH (Schmitt trigger positive going threshold) V Output low OL voltage ...
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... AC ELECTRICAL CHARACTERISTICS READ CYCLE Symbol Figure 1/t 8 Clock frequency at RFW-D100 input - CLK1 OSC pulse width RDPW low to RD low CSRD t 8 ADDRESS valid to RD low ADRD low to DATA valid RDDV t 8 DATA float after RD RHDT t 8 DATA hold after RD DHAR t 8 Time between consecutive RD pulses ...
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... RFW-D100 Vishay RFWaves CS WR ADDRESS t ADWR t DVWR DATA www.vishay.com For more information please contact: RFTransceivers@vishay.com 28 t CSWR t WRWR t WRPW t AVAW t DVAW Figure 10. The RFW-D100 Write Cycle Document Number 84675 Rev. 1.1, 22-Jan-07 ...
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... LQFR-44 PACKAGE DESCRIPTION Document Number 84675 For more information please contact: RFTransceivers@vishay.com Rev. 1.1, 22-Jan-07 RFW-D100 Vishay RFWaves www.vishay.com 29 ...
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... Vishay RFWaves APPENDIX A - RADIO SIGNAL STRENGTH INDICATOR (RSSI) General Description: The RFW-D100 includes a special built-in Analog module that supports Carrier detection. The principle of operation is rather simple. In order to maintain a ‘well-behaved’ protocol under a CSMA assumption, It would be highly efficient if each node could detect whether “ ...
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... Operating voltage Current consumption Quiescent current Comparator bias current Reference voltage Hysteresis envelope Document Number 84675 For more information please contact: RFTransceivers@vishay.com Rev. 1.1, 22-Jan-07 VX RFW-D100 Internal Block Rup Vcc - Comp + Vref Rdown Inv Figure 12. The RSSI Block Diagram As mentioned, the slicer includes an internal ...
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... Using 8 bits for DST ID means that each network will have at most 256 participants. The location of the DST ID field is recommended to be constant in the packet header, since it enables the RFW-D100 to filter packets according to their DST ID. Few of the address are preserved in the RFW-D100 for multicast. www.vishay.com For more information please contact: RFTransceivers@vishay.com 32 SRC ID – ...
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... Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’ ...