RFW-D100 Vishay, RFW-D100 Datasheet - Page 24

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFW-D100
Vishay RFWaves
INTERRUPT REGISTERS
Interrupt Enable Register (IER)
For all flags in this register:
1 – Enable.
0 – Disable.
Bit 0: LOCK_IN
This flag enables/disables the LOCK_IN interrupt.
PREAMBLE + NODE_ID + NET_ID identified
correctly, triggers LOCK IN interrupt.
Bit 1: LOCK_OUT
This flag enables/disables the LOCK_OUT interrupt.
Normal ending of received packet triggers LOCK_OUT
interrupt. Normal ending means that all the bytes of the
packets were received.
Bit 2: LINK_DIS
This flag enables/disables the LINK_DIS interrupt.
The zero counter capacitor discharge triggers the
LINK_DIS interrupt.
Bit 3: RX_OF
This flag enables/disables the RX_OF interrupt.
End of received packet triggers RX_OF interrupt.
Interrupt Identification Register (IIR)
This is a read only register.
This register shows the enabled interrupt events that
occurred, since the last time it was read. Each time the
register is read, all the flags are cleared. This register
is only cleared by global reset (RST) or by reading from
it. Each time an interrupt occurs, its corresponding flag
is set.
Bit 0: LOCK_IN
This bit reflects the LOCK_IN flag interrupt when
enabled by IER.
LOCK_IN interrupt is invoked whenever a PREAMBLE
+ NET_ID + NODE_ID is recognized.
If NET_ID is disabled, then a received PREAMBLE +
NODE_ID invokes the interrupt.
If NODE_ID is disabled, then a received PREAMBLE
+ NET_ID invokes the interrupt.
If NET_ID and NODE_ID are disabled, then a received
PREAMBLE invokes the interrupt.
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24
Name
Name
IER
IIR
Bit 7
Bit 7
CS
CS
TX_AE
TX AE
Bit 6
Bit 6
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RX AF
RX AF
Bit 5
Bit 5
TX EMPTY
TX EMPTY
Bit 4
Bit 4
This register is a read/write register.
This register determines whether each of the events
mentioned below will cause an interrupt.
Bit 4: TX_EMPTY
This
(Transmitter Empty) interrupt.
TX_EMPTY interrupt tells the MCU that the transmitter
has just finished transmitting a packet. The RFW-D100
goes to RX mode after finishing the transmission of a
packet.
Bit 5: RX_AF
This flag enables/disables the RX_AF interrupt.
The RX_AF interrupt is triggered when the RX_FIFO
AF flag goes from ‘0’ to ‘1’.
Bit 6: TX_AE
This flag enables/disables the TX_AE interrupt.
The TX_AE interrupt is triggered when the TX_FIFO
AE flag goes from ‘0’ to ‘1’.
Bit 7: CS
This flag enables/disables the CS interrupt.
A negative edge of CS flag in SSR triggers CS
interrupt.
Default Value: 0 x 00
LOCK_IN interrupt signals the MCU that a new packet
is started to be received.
Bit 1: LOCK_OUT
This bit reflects the LOCK_OUT flag interrupt when
enabled by IER.
LOCK_OUT interrupt is invoked whenever the
RFW-D100 has finished receiving a packet. The end of
the packet is determined according to the packet size.
Bit 2: LINK_DIS
This interrupt is invoked by the zero counter capacitor
discharge mechanism.
The actual discharge mechanism can be disabled, but
the interrupt can occur if it is enabled.
Bit 3: RX_OF
This bit reflects the RX_OF (over flow) flag interrupt
when enabled by IER.
RX_OF
RX_OF
BIt 3
BIt 3
flag
enables/disables
LINK_DIS
LINK_DIS
BIt 2
BIt 2
LOCK OUT
LOCK OUT
Bit 1
Bit 1
Document Number 84675
the
Rev. 1.1, 22-Jan-07
TX_EMPTY
LOCK IN
LOCK IN
Bit 0
Bit 0