RFW-D100 Vishay, RFW-D100 Datasheet - Page 13

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RX_FIFO, it can only read from it.
The MCU has three ways of learning about the
RX_FIFO status:
The RX_AF interrupt should invoke the MCU to read
from the RX_FIFO. Using the almost full event gives
the MCU 32 µsec (4 bytes * 8 µsec) to respond before
it loses data, assuming a bit rate of 1 Mbps. It uses
most of the RX_FIFO size, even if the response
latency of the MCU is very short. Should the MCU not
respond properly to the almost full event, and an input
byte is written to the RX_FIFO when it is full, then this
byte will be discarded and will not be written to the
RX_FIFO.
The threshold that determines when RX_AF interrupt
is
(FIFO_FLAGS) is set to ‘0’, RX_AF interrupt is invoked
when RX_FIFO contains 12 bytes. When SCR4(3)
(FIFO_FLAGS) is set to ‘1’, RX_AF interrupt is invoked
when RX_FIFO contains 8 bytes. The last mode
should be used with a slow MCU or long response time
for interrupts.
LOCK_OUT interrupt should also trigger the MCU to
read from the RX_FIFO. If a packet has ended and the
RX_AF interrupt was not invoked, the MCU should be
triggered by the LOCK_OUT interrupt.
When using NODE_ID and/or NET_ID filters, the data
of a new incoming packet is not reachable for the MCU
until NODE_ID and/or NET_ID has been identified
correctly. RFSR is only updated after NODE_ID and/or
NET_ID has been identified correctly. On the other
hand, the internal RX_FIFO counter is incremented
with no regard to NET_ID and NODE_ID. This may
cause an RX_AF interrupt while RFSR is lower than 12
(when SCR4(3)=‘0’). In the worst case scenario,
RX_FIFO contains 7 bytes from previously received
packets. The NODE_ID is enabled and set to be the 5
Document Number 84675
Rev. 1.1, 22-Jan-07
• The RX_FIFO Status Register (RFSR) – contains
• RX_FIFO Almost Full Interrupt (RX_AF) – INT pin.
• RX_FIFO Overflow Interrupt – bit RX_OF in IER
the number of bytes in the RX_FIFO. Each
incoming byte increment RFSR, and each read
from RX_BYTE by MCU decrement RFSR.
If configured appropriately, the INT pin will be “1”
each time RX_FIFO is almost full. This invokes an
MCU interrupt if the INT pin is connected to the
MCU’s external interrupt pin.
indicates when an overflow event has occurred. If a
received byte is written to a full RX_FIFO, then the
received byte is discarded and the RX_OF interrupt
is invoked. This interrupt tells the user that at least
one byte has been lost from the currently received
packet.
invoked
is
programmable.
For more information please contact: [e-mail]
When
SCR4(3)
th
byte in each packet. In this case, the RX_AF interrupt
can be invoked when there are only 7 bytes in
RX_FIFO available for the MCU (RFSR=7).
TX_FIFO
The purpose of TX_FIFO is to have an output buffer
between the MCU and the serial output towards the
RFW122. This reduces the real time burden of the
MCU in a transmitting process. The TX_FIFO enables
the MCU, theoretically, to write to the TX_FIFO every
128 µsec instead of every 8 µsec, as is the case with a
regular 8-bit shift register.
The interface to the TX_FIFO is similar to all the other
write-only registers in the RFW-D100.
The MCU has three ways to learn about the TX_FIFO
status:
INTERRUPT DRIVER
The INT output pin is the summation of all interrupt
sources in the RFW-D100. Whenever an interrupt
event has occurred and is enabled (IER), INT will go
from low to high. INT will stay high until IIR register is
read. IIR register contains all the interrupt events that
have occurred since the last read. It shows the event
only for enabled interrupts. If an interrupt is disabled,
even if the event that invoked this interrupt has
occurred, then the interrupt flag will be low. IER
register is used to enable/disable each of the interrupt.
SCR4(0) enables/disables all the interrupts.
• TX_FIFO Status Register (TFSR) – indicates the
• TX_FIFO almost Empty Interrupt (TX_AE) – when
• TX_FIFO underflow flag (TX_UF in SSR) – If the
number of bytes in the TX_FIFO.
SCR4(3) equals ‘0’, the TX_AE interrupt is invoked
whenever the number of bytes in TX_FIFO goes
from 5 to 4 (when SCR4(3)=‘1’ it is from 9 to 8). The
TX_AE tells the MCU that it should reload the
TX_FIFO if it still has bytes from the current packet,
since the RFW-D100 is about to finish transmitting
the data in TX_FIFO. It gives the MCU 32 µsec to
respond to reload the TX_FIFO. For slow MCUs or
when response time for interrupt is long, the
interrupt threshold can be set to 8 bytes in TX_FIFO
(by SCR4(3)=‘1’). This gives the MCU up to 64
µsec to respond to the TX_AE.
RFW-D100 tries to read from an empty TX_FIFO,
the RFW-D100 stops transmitting. The TX_EMPTY
interrupt is invoked and TX_UF flag in SSR is set to
‘1’. TX_UF flag indicates the transmission has
ended abnormally, since the RFW-D100 has tried
to read from an empty TX_FIFO.
Vishay RFWaves
RFW-D100
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