RFW-D100 Vishay, RFW-D100 Datasheet - Page 18

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFW-D100
Vishay RFWaves
FREE RUN COUNTER – LOW (FRC-L)
FRC is a wrap-around 12 bit counter incremented
WDT_CLK clock.
Whenever the counter reaches its overflow value
(FRC-H(4-0), FRC-L), a pulse is generated in the WDT
pin, according to FRC-H(4:6). This counter can
implement a kind of watchdog timer for the MCU.
This register contains the 8 least significant bits of the
16 bits overflow value.
Default Value: 0 x FF.
FREE RUN COUNTER – HIGH (FRC-H)
FRC-H[3-0]:
FRC is a wrap-around 12 bit counter incremented
WDT_CLK clock.
PACKET PARAMETER REGISTER (PPR)
This is a read/write register.
It contains control flags of the transmitted and received
packet structure.
Default Value: 0 x 3A.
Bits 0-2: Refresh Bit - RB [2:0]
The value of the refresh bit is determined by the value
of the reference capacitor.
Bit 4, 3: CRC [0:1]
These bits control the CRC operation for both transmit
and receive mode:
Bit 5: FIXED
Controls the packet mode.
When FIXED bit is high, the RFW-D100 sends and
receives packets with a fixed size/length that is
specified in the Packet Size Register (PSR).
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18
Refresh Bit
Refresh bit is added to every byte, no matter what its content.
Refresh bit is added if 1 byte equals x“00”.
Refresh bit is added if 2 successive bytes equal x“00”.
Refresh bit is added if 3 successive bytes equal x“00”.
Refresh bit is added if 4 successive bytes equal x“00”.
Refresh bit is added if 5 successive bytes equal x“00”.
Refresh bit is added if 6 successive bytes equal x“00”.
Refresh bit is added if 7 successive bytes equal x“00”.
Name
PPR
No CRC
CRC 16
CRC 8
CRC 8
CRC
NET ID_EN
Bit 7
NODE ID_EN
Bit 4
0
0
1
1
Bit 6
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FIXED
Bit 5
Bit 3
0
1
0
1
CRC1
Bit 4
Whenever the counter reaches its overflow value
(FRC-H(3-0), FRC-L), a pulse is generated in the WDT
pin. This counter can implement a kind of watchdog
timer for the MCU.
Bit 0-3 in this register contains the 4 most significant
bits of the 12-bits overflow value.
FRC-H[6-4]: pulse count
These bits determine the watchdog pulse width.
The pulse width is: 2^(FRC_H(6-4) x RC oscillator
periods.
It is important to emphasize that the clock source for
the WDT pulse is the RC oscillator and not the
pre-scaled clock.
Default Value: 0 x FF.
These bits determine the maximum number of
successive “zero” bytes allowed before an added “one”
bit is stuffed to the packet by the transmitter state
machine. The reason for this feature is to keep the
RFW122 reference capacitor charged, thus retaining
the receiver’s sensitivity.
When FIXED bit is low, the packet size is variable. The
size is specified in the header of the incoming or
outgoing packets. The location of the packet size field
is specified in the LCR register.
Bit 6: NODE_ID_EN
This is NODE_ID enable/disable bit.
When NODE_ID_EN is 1, NODE_ID filter is enabled
according to LCR, BIR.
When NODE_ID_EN is 0, NODE_ID filter is disabled.
Bit 7: NET_ID_EN
This is NET_ID enable/disable bit.
When NET_ID_EN is 1, NET_ID filter is enabled
according to LCR, NIR.
When NET_ID_EN is 0, NET_ID filter is disabled.
CRC0
Bit 3
Bit 2
RB-2
Bit 2
0
0
0
0
1
1
1
1
Bit 1
RB-1
Bit 1
Document Number 84675
0
0
1
0
0
0
1
1
Rev. 1.1, 22-Jan-07
Bit 0
RB-0
Bit 0
0
1
0
1
0
1
0
1