RFW-D100 Vishay, RFW-D100 Datasheet - Page 16

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

RFW-D100
Vishay RFWaves
RFWAVES CARRIER SENSE ALGORITHM:
Assuming our bit rate is 1 Mbps. According to the
described bit structure (section 0 Bit Structure), the
time difference between two raising edges on
DATA_IO must be an integer number of 1 µsec. If we
take into account the frequency deviation between the
two RFW-D100 oscillators, the time difference
between two raising edges is 1 µsec ± Δ. The Δ
depends on the frequency deviation between the two
RFW-D100 oscillators. The RFW-D100 uses this qual-
ity in its carrier sense algorithm. If an N (N=(CSR(0:3)
x 2) + 2) number of “1” bits, where each is preceded by
at least one “0” bit, is received with time difference of
an integer number of 1 µsec between two consecutive
“1” bits, then CS flag in SSR equals ‘1’. Basically, the
RFW-D100 counts “0” to “1” transits on DATA_IO
input, where the time difference between two transits
In the example shown in Figure 8, at time (1) a new “1”
bit is received after a “0” bit was received. Thus,
CNT_ONE equals 1 and ZERO_CNT is reset to 0. At
time (2), a “0” bit is received, so the ZERO_CNT is
incremented. At time (3), a “1” is received after a “0” bit
was received. Thus ONE_CNT is incremented and
ZERO_CNT is reset. At time (4) a “1” bit is received
after a “1” bit, thus there is no change in any counter.
At time (6) a “1” bit is received out of the allowed
window, so ONE_CNT is reset to 1. CSR register is
used to configure the carrier sense algorithm sensitiv-
ity. CSR register determines the number of “1” bits that
are required in order to decide that a carrier exists.
CSR also determines the number of successive “0”
bits that reset the carrier sense state machine.
In SSR register, bit CS notifies whether a carrier was
identified. Carrier sense can also be used as an
interrupt. When CS in SSR goes from ‘1’ to ‘0’, i.e. the
transmission has stopped and a CS interrupt is
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16
DATA_IO
Signal
ZERO_CNT=1
ONE_CNT=0
(0)
1 µs
ZERO_CNT=0
ONE_CNT=1
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(1)
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1 µs
Figure 8. RFWaves Carrier Sense Example
ZERO_CNT=1
ONE_CNT=1
(2)
2 * 1 µs
ZERO_CNT=0
ONE_CNT=2
(3)
should be an integer number (≥ 2) of 1 µsec. The
number of consecutive “1” bits that obey this rule is
counted in the following example (Figure 8) in
ONE_CNT counter. ONE_CNT is incremented only if a
“1” bit that comes after a “0” bit is received, where the
time gap between the “1” bit and the preceding “1” bit
is as mentioned above. If the time difference between
two consecutive “1” bits is out of the allowed deviation,
then the ONE_CNT is reset. ONE_CNT is also reset if
the number of consecutive “0” exceeds (CSR(4:7) x 2)
+ 2, where CSR is the Carrier Sense Register (see 0
Carrier Sense Register (CSR)). The number of
consecutive “0” bits from the last “1” bit received is
counted in ZERO_CNT. ZERO_CNT is reset each
time “1” bit is received.
Both M and N values are determined in CSR register
(CSR(7:4) and CSR(3:0) accordingly).
invoked (if enabled in IER). The purpose of this
interrupt is to inform the MCU that the channel is free
again.
If the RFW-D100 identifies a packet, the carrier sense
algorithm halts. When the RFW-D100 is in RX mode
and LOCK flag in SSR is “0”, CS mechanism is
working. When LOCK flag in SSR is “1”, CS
mechanism is not working, since CS flag does not add
any information because a PREAMBLE was identified,
already. After a PREAMBLE is identified CS in SSR
equals ‘1’.
RECEIVER REFERENCE CAPACITOR DIS-
CHARGE
The
mechanisms for receiver capacitor discharge:
• At the end of each received packet
• Zero counter
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ZERO_CNT=0
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ONE_CNT=2
RFW-D100
(4)
1 µs
ZERO_CNT=1
ONE_CNT=2
implements
(5)
ZERO_CNT=0
1 µs
ONE_CNT=1
(6)
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Document Number 84675
two
Rev. 1.1, 22-Jan-07
independent