RFW-D100 Vishay, RFW-D100 Datasheet - Page 19

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SYSTEM CONTROL REGISTER 1 (SCR1)
This register is a general control register. It is a read/
write register.
Bits 0-2: RT [0:2]
These bits determine the division rate (DIV_VALUE) of
the RC oscillator clock. The divided clock (RC
oscillator/DIV_VALUE) drives the WDT module (see
WDT chapter).
The DIV_VALUE, i.e. the division rate of watchdog
external
(1,2,4,8,…,64,128).
DIV_VALUE = 2^(RT[0:2]).
Bit 3: WDT_EN
This is the watchdog (WDT) enable/disable control bit.
When WDT is ‘1’ – the WDT module is enabled. The
WDT counter runs, and if it equals its overflow values
it generates a pulse on the WDT output pin.
When WDT is ‘0’ – the WDT module is disabled.
SYSTEM CONTROL REGISTER 2 (SCR2)
This register controls the RFW-D100 operation modes.
This register is a read/write register.
Bit 0: TX_RX
Controls the transceiver mode: receive mode or
transmit mode.
When TX_RX is low – the RFW-D100 is in receive
mode (default mode). The output pin TX_RX is set to
‘0’. The RFW-D100 searches for a PREAMBLE. If
PREAMBLE is found, it handles the process of receiv-
ing a packet.
There two cases in which SCR2(0) equals ‘0’ but
TX_RX output pin is in TX mode (‘1’):
1. If a SCR3(7) is set, then the RFW-D100 goes to RX
2. The capacitor discharge can change the output pin
Document Number 84675
Rev. 1.1, 22-Jan-07
mode and the output pin TX_RX goes to TX mode.
TX_RX to TX mode even if RFW-D100 are in RX
mode. In this case, the output pin TX_RX will be in
TX mode for a short duration and then return to RX
mode.
Name
Name
SCR1
SCR2
oscillator,
PRE MASK 2 PRE MASK 1 PRE MASK 0
Bit 7
Bit 7
is
Bit 6
Bit 6
by
For more information please contact: [e-mail]
powers
CMP EN
Bit 5
Bit 5
of
2
STOP RX
RC_EN
Bit 4
Bit 4
The control registers SCR1(2:0) (RT(2:0)), FRC-L and
FRC-H should be modified only when WDT_EN is ‘0’,
i.e. the WDT is disabled.
Bit 4: RC_EN
This bit controls the RC oscillator module.
When RC_EN is ‘1’ – the RC oscillator is enabled.
When RC_EN is ‘0’ – the RC oscillator is disabled.
Enabling the RC oscillator is a preliminary condition to
work with the WDT.
Bit 5: CMP_EN
This bit controls the analog comparator module
(RSSI).
When CMP_EN is ‘1’ – the comparator is enabled.
When CMP_EN is ‘0’ – the comparator is disabled.
Default Value: 0 x 00.
When TX_RX is high – the RFW-D100 is in transmit
mode. The output pin TX_RX is set to ‘1’. The
RFW-D100 handles the process of transmitting a
packet according to the data in the TX_FIFO. When it
finishes transmitting the packet, it automatically goes
back to receive mode. When RDW-D100 goes back to
receive mode, SCR2(0) (TX_RX) is ‘0’ again.
Bit 1: SEARCH_EN
Preamble search enable bit.
When 1: Enables the search for PREAMBLE in receive
mode.
When 0: Disables the search for PREAMBLE in
receive mode (used when user configures the
RFW-D100 while in default receive mode).
This bit’s default value is ‘0’. It must be set to ‘1’ in
order to start receiving a packet.
When modifying control registers in the RFW-D100,
this register must be set to ‘0’. Changing the
RFW-D100’s configuration must be done when the
RFW-D100 is in RX mode and no packet is being
received and the search for a PREAMBLE is disabled.
WDT EN
TX FIFO
RESET
Bit 3
Bit 3
RX FIFO
RESET
Bit 2
Bit 2
RT2
Vishay RFWaves
SEARCH EN
Bit 1
Bit 1
RT1
RFW-D100
www.vishay.com
TX_RX
Bit 0
Bit 0
RT0
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