CS5126-KL Cirrus Logic Inc, CS5126-KL Datasheet
CS5126-KL
Specifications of CS5126-KL
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CS5126-KL Summary of contents
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... When the CS5126 is configured for 2X oversam- pling, digital post-filtering bandlimits this white noise to 20 kHz, increasing dynamic range to 95 dB. ORDERING INFORMATION CS5126-KP 0° to 70° C CS5126-KL 0° to 70° C Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved) CS5126 28-pin Plastic DIP 28-pin PLCC MAR ‘ ...
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... VREF = 4.5V; Analog Source Impedance = 200 ; clk Symbol S/(N+D) THD DR V n(ic) (Note FSE BPO t apt t ajt (Note 2) C (Note (Notes (Note 5) PSR Min Typ Max - - 0.001 1 0. 100 - 200 -18 - -12 - 260 350 CS5126 Units Bits - LSB rms - LSB - LSB - DS32F1 ...
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... Analog Reference Voltage Analog Input Voltage Notes: 7. All voltages with respect to ground. 8. The CS5126 can accept input voltages up to the analog supplies (VA+, VA-). It will produce an output of all 1’s for inputs above VREF and all 0’s for inputs below -VREF. ABSOLUTE MAXIMUM RATINGS ...
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... RST t cal STBY t drrs Reset and Calibration Timing HOLD t dhs t sclk SDATA SCLK Data Transmit Start Timing CS5126 10%; Units - +50 ns clk - clk ns clk ns clk - MSB DS32F1 ...
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... SRAM, and can be recalibrated at any later time. SYSTEM DESIGN WITH THE CS5126 All timing and control inputs to the CS5126 can be easily generated from a master system clock. The CS5126 outputs serial data and a variety of digital outputs which can be used to control an external sample/hold amplifier for simultaneous sampling ...
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... RST rises to guarantee an accurate calibration. Later, the CS5126 may be reset at any time to initiate a single full calibration. Reset overrides all other functions. If reset, the CS5126 will clear and initiate a new calibration cycle mid- conversion or midcalibration ...
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... F Figure 2. Stereo Mode Connection Diagram STEREO MODE PERFORMANCE As illustrated in Figure 4, the CS5126 typically provides 92dB S/(N+D) and 0.001% THD. Un- like conventional successive-approximation ADC’s, the CS5126’s signal-to-noise and dy- namic range are not limited by differential non- linearities (DNL) caused by calibration errors. ...
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... Relative to Full Scale -100dB -120dB 1 kHz Input Frequency Figure 4. FFT Plot of CS5126 in Stereo Mode (Left Channel with 1 kHz, Full-Scale Input) Differential Nonlinearity The self-calibration scheme utilized in the CS5126 features a calibration resolution of 1/4 LSB, or 18-bits. This ideally yields DNL of 1/4 LSB, with code widths ranging from 3/4 to 5/4 LSB’ ...
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... Since the CS5126 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converter’s HOLD input falls ...
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... Figure 8a. The right channel input at AINR will appear the CS5126 resulting current flowing through the internal MOS switches. Sampling distortion can likewise be improved for both channels using the SSH1 output as shown in Figure 8b ...
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... Due to its on-chip self-calibration scheme, the CS5126’s dynamic range is limited only by white broadband noise rather than signal-depend- ent DNL errors. Therefore, the CS5126 picks up a full 3dB improvement in dynamic range to 95dB when implemented in 2X oversampling schemes. Oversampling and digital filtering also enhance the ADC’ ...
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... SLEEP is brought high. Left Analog In Figure 11. High-Slew Monaural Connections -20dB -40dB -60dB Signal Amplitude -80dB Relative to Full Scale -100dB -120dB Figure 12. FFT Plot of CS5126 in Monaural 2X Over- CS5126 512 f s 256 f s CKIN OBCK WDCK f s LRCK DOL DATA IN SM5805 ...
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... CS501X/CSZ511X Series of A/D Convert- ers" is available which describes the dynamic load conditions presented by the VREF input on Crystal’s self-calibrating SAR A/D converters (including the CS5126). As the CS5126 se- quences through bit decisions it switches por- tions of the capacitor array to the VREF pin in accordance with the successive-approximation algorithm ...
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... The CS5126 can operate with a wide range of reference voltages, but signal-to-noise perform- ance is maximized by using as wide a signal range as possible. The recommended reference voltage is 4.5 volts. The CS5126 can actually accept reference voltages up to the positive ana- log supply. However, as the reference voltage approaches VA+ the external drive requirements may increase at VREF ...
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... CS5126. The CDB5126 evaluation board is available for the CS5126, which avoids the need to design, build, and debug a high-preci- sion PC board to initially characterize the part. The board comes with a socketed CS5126, and Schematic & Layout Review Service Confirm Optimum Confirm Optimum Schematic & ...
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... TRKR 10 20 SSH1 SSH2 HOLD L/R SCLK CS5126 SLEEP SLEEP (LOW POWER) MODE TST4 TEST TST3 TEST VA+ POSITIVE ANALOG POWER AINR RIGHT CHANNEL ANALOG INPUT VA- NEGATIVE ANALOG POWER AGND ANALOG GROUND REFBUF REFERENCE BUFFER VREF VOLTAGE REFERENCE AINL LEFT CHANNEL ANALOG INPUT ...
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... Digital Inputs HOLD - Hold, PIN 12. A falling transition on this pin sets the CS5126 to the hold state and initiates a conversion. This input must remain low at least one master clock cycle plus 50ns. L/R - Left/Right Input Channel Select, PIN 13. Status at the end of a conversion cycle determines which analog input channel will be acquired for the next conversion cycle ...
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... Reference buffer output. A 0.1 F ceramic capacitor must be tied between this pin and VA-. Miscellaneous Connection, PIN 4. Must be left floating for proper operation. TST1, TST2, TST3, TST4 - Test, PINS 17, 18, 26, 27. Allow access to the CS5126’s test functions which are reserved for factory use. Must be tied to VD+. 18 CS5126 DS32F1 ...
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... Effectively a sampling delay which can be nulled by advancing the sampling signal. Units in nanosec- onds. Aperture Jitter - The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. DS32F1 CS5126 19 ...
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Notes • ...
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... Evaluation Board for CS5126 Features l Serial to Parallel Conversion l All Timing Signals Provided l Adjustable Voltage Reference l ±5 V Regulators l Digital and Analog Patch Areas I 0V Analog Patch Area AGND Voltage VREF Reference REFBUF VA- AINL AINL AINR AINR BP/UP SLEEP Mode TEST Select Switches ...
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... V in the bi- ref impedance. To try the unbuffered LT1019-5 di- rectly, solder in J2 and cut the VREF trace. Alternatively the shunt reference based reference schematic given in the CS5126 data sheet can be evaluated by adding it to the analog patch area. 78L05 +15V U4 IN OUT ...
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... M 121 k V+ 0.01 F ceramic 0.01 F ceramic V- +15V C6 0 OP27 0 0. 0.1 F -15V Figure 3. Voltage Reference CDB5126 200 V out 1 nF C0G ceramic Notes and offset adjust are optional. 2) Offset adjustment range with values shown. TP1 0.1 F TP4 22 U1 CS5126 VREF AGND 23 ...
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... ADC are elevated to can be done by inserting 22 with the regulator (U4 and U5) common leads. Master Clock The CS5126 requires an external 24.576 MHz clock for a 96 kHz sample rate. A 24.576 MHz clock oscillator module (U6) is provided. An ex- ternal clock can also be selected by P1, via a ...
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... Sampling Clock Generation Logic The CS5126 requires an external serial clock to clock out the data. The CDB5126 board has the logic necessary to generate the master clock, HOLD, L/R, and SCLK to allow fast evaluation of the ADC. In most systems, these timing sig- nals will be available from the main timing section, typically generated by a logic array of some variety ...
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P9 +5VL C5 SDATA (U1) 74HC00 TRKL (U1) 10 U11 TRKR (U1 +5VL 0 RST Shift CLK Latch ...
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... Connects TRKL & TRKR to U10B, the handshake flip-flop Connects the on-board data ready signal to U10B. P12 0 - Allows selection of the DRDY signals for alternate channels Connects the TRKL & TRKR to U11, pin 13. Factory default state for CS5126 DS32DB5 Table 1. Solder Link Options Table 2. Shorting Plug Selectable Options CDB5126 ...
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... This resets U10B for the next word. This handshake can be disabled by setting P8 jumper to position 1. DIP Switches Figure 7 and Table 3 shows the DIP switch se- lectable options. SLEEP mode set at logic "1" for CS5126 set at logic "1" for CS5126 OPEN Logic "0" CLOSED / Logic "1" = OFF = OPEN Figure 7 ...
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... Miscellaneous Hints on Using the Evaluation Board Always hit the reset button after powering-up the board. The CS5126 is self calibrating and require the reset signal to initiate the calibration proce- dure. P4 controls the ADC input mux. This is used to set the mux to be continuously connected to one channel toggling between two channels ...
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Figure 9. CDB5126 Component Layout CDB5126 DS32DB5 ...
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DS32DB5 Notes CDB5126 31 ...
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