CS5126-KL Cirrus Logic Inc, CS5126-KL Datasheet - Page 27

• Manufacturer Part Number: CS5126-KL
• Description: ADC Single SAR 100KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5126-KL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar

DS32DB5
J1
J2
J4
P1
P2
P3
P4
P6
P7
P8
P9
P10
P11
P12
-
-
-
Factory default state for CS5126
Joins analog ground to digital ground on the board.
Joins LT1019-5 reference directly to the VREF pin on the ADC. Before doing this, break the connection
Connects an external clock to CLKIN on the ADC.
0 - Select external clock via BNC connector
1 - Select on-board clock generated by U6.
0 - Select on-board generated HOLD.
1 - Select external HOLD via BNC connector.
1 - Drive L/R select at 48 kHz from the on-board timing generator.
2 - Pull L/R select pin low, selecting the right channel only.
0 - Connects the on-board Data Ready signal to the shift registers.
1 - Connects the NAND gate outputs (U11, pin 11) to the shift registers.
1 - Connects the un-latched on-board Data Ready signal to P5.
2 - Connects TRKL and TRKR ANDED together to P5. This signal can be used as an "End of Convert"
3 - Connects TRKL to P5.
4 - Connects TRKR to P5.
0 - Causes the on-board Data Ready generating circuit to flag data ready every conversion.
1 - Causes the on-board Data Ready generating circuit to flag data ready every left conversion. P4 must
2 - Causes the on-board Data Ready generating circuit to flag data ready every right conversion. P4 must
0 - Connects TRKL & TRKR to U10B, the handshake flip-flop.
1 - Connects the on-board data ready signal to U10B.
0 - Allows selection of the DRDY signals for alternate channels.
1 - Connects the TRKL & TRKR to U11, pin 13.
between R3 and the ADC VREF pin by using a twist drill to remove the central feedthrough. This option
allows evaluation of different reference configurations.
Connect SCLK to on-board shift registers.
Pull L R select pin high, selecting the left channel only.
Connect the OE pins of the shift registers to ground. Permanently enables the 3-state output buffers.
Connects the on-board generated SCLK to the rest of the on-board circuitry.
indicator.
be in position 1 for this to work.
be in position 1 for this to work.
Table 2. Shorting Plug Selectable Options
Table 1. Solder Link Options
CDB5126
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