CS5126-KL Cirrus Logic Inc, CS5126-KL Datasheet - Page 11
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CS5126-KL
Manufacturer Part Number
CS5126-KL
Description
ADC Single SAR 100KSPS 16-Bit Serial 28-Pin PLCC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5126-KL.pdf
(32 pages)
Specifications of CS5126-KL
Package
28PLCC
Resolution
16 Bit
Sampling Rate
100 KSPS
Architecture
SAR
Number Of Adcs
1
Number Of Analog Inputs
2
Digital Interface Type
Serial
Input Type
Voltage
Polarity Of Input Voltage
Bipolar
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larly, the acquisition time for the external sam-
ple/hold amplifiers must not exceed the mini-
mum conversion time of 192 master clock cycles
(7.8 s for 48kHz stereo sampling).
Oversampling
The CS5126 can alternatively be used to over-
sample one channel (monaural) by 2X simply by
tying the L/R input high or low. This moves
much of the anti-alias burden from analog filters
to digital post-filtering. The analog filters’ cor-
ner can be pushed out in frequency with lower
roll-off, allowing lower passband ripple and
more linear phase in the audioband. Digital FIR
filtering, meanwhile, can be used to implement
high roll-off filters with ultra-low passband rip-
ple and perfectly linear phase.
Oversampling not only improves system-level
filtering performance, but it also enhances the
ADC’s dynamic range and distortion charac-
teristics. All noise energy in a sampled, digital
signal aliases into the baseband between dc and
one-half the sampling rate. For an ideal succes-
DS32F1
Analog
Input
+5V
-5V
Anti Alias
Reference
Voltage
Filter
+
Figure 9. Monaural 2X Oversampling Connections
1 F
0.1 F
+ 1 F
200
* AINR can alternatively be used
1nF
0.1 F
0.1 F
with L/R grounded
AINL*
AINR
VREF
AGND
REFBUF
VA+
VA-
sive-approximation ADC the noise spectral con-
tent is white. Therefore, in a 2X oversampling
scheme such as 96kHz sampling the ADC’s
noise will be be spread uniformly from dc to
48kHz. Digital post-filtering then rejects noise
outside of the 20kHz or 22kHz bandwidth, re-
sulting in improved signal-to-noise and dynamic
range. For a white noise spectrum, a 2X reduc-
tion in bandwidth yields a 3dB improvement in
dynamic range.
Due to its on-chip self-calibration scheme, the
CS5126’s dynamic range is limited only by
white broadband noise rather than signal-depend-
ent DNL errors. Therefore, the CS5126 picks up
a full 3dB improvement in dynamic range to
95dB when implemented in 2X oversampling
schemes.
Oversampling and digital filtering also enhance
the ADC’s distortion performance. Consider for
example a full-scale 15kHz input signal to the
CS5126 sampling at 96kHz. Sampling distortion
produces THD of approximately 0.005% (86dB)
at the converter’s output. Most of the distortion
energy resides in the second and third harmonics
CS5126
10
10
SDATA
SLEEP
VD+
VD-
CLKIN
DGND
HOLD
SCLK
L/R
0.1 F
0.1 F
+5V*
f
f
f
clk
clk
clk
+
/256
/16
1 F
+ 1 F
CS5126
11