CS5126-KL Cirrus Logic Inc, CS5126-KL Datasheet - Page 4

• Manufacturer Part Number: CS5126-KL
• Description: ADC Single SAR 100KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5126-KL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar

SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0V, Logic 1 = VD+; C
Notes: 10. SSH2 only works correctly if HOLD falling edge is within 30ns of L/R edge OR if HOLD falling edge
4
Master Clock Period
HOLD to SSH2 Falling
HOLD to TRKL, TRKR
HOLD to TRKL, TRKR
RST Pulse Width
RST to STBY Falling
RST Rising to STBY Rising
HOLD Pulse Width
HOLD to L/R Edge
SCLK period
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Falling to SDATA Valid
HOLD Falling to SDATA Valid
L/R
HOLD
Channel Selection Timing
HOLD (i)
SSH2 (o)
TRKL (o)
TRKR (o)
occurs between 30ns before HOLD rises to 192 t
Control Output Timing
t
hold
t
Parameter
dhlri
t
dfsh2
t
drsh
SSH1 Falling
SSH1, SSH2 Rising
t
dfsh1
L
SCLK
SDATA
= 50 pF)
Serial Data Timing
(T
(Note 10)
A
(Note 10) t
t
dss
= 25 C; VA+, VD+ = 5V
t
sclkl
clk
t
Symbol
sclkh
after HOLD falls.
t
t
t
dfsh2
dfsh1
t
t
t
t
t
sclkh
t
t
t
drsh
t
sclkl
t
hold
dhlri
drrs
sclk
dhs
dss
clk
cal
rst
RST
STBY
t
sclk
Reset and Calibration Timing
2t
198t
clk
Min
150
200
-30
40
50
50
-
-
-
-
-
-
+50
clk
t
drrs
Data Transmit Start Timing
HOLD
SDATA
SCLK
10%; VA-, VD- = -5V
34,584,480
t
rst
Typ
100
100
140
80
80
-
-
-
-
-
-
-
-
t
dhs
t
cal
214t
192t
192t
Max
140
200
clk
CS5126
-
-
-
-
-
-
-
-
-
MSB
clk
clk
+50
DS32F1
10%;
Units
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk