CS5126-KL Cirrus Logic Inc, CS5126-KL Datasheet - Page 5

• Manufacturer Part Number: CS5126-KL
• Description: ADC Single SAR 100KSPS 16-Bit Serial 28-Pin PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5126-KL

• Package: 28PLCC
• Resolution: 16 Bit
• Sampling Rate: 100 KSPS
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar

GENERAL DESCRIPTION
The CS5126 is a 2-channel, 100kHz A/D con-
verter designed specifically for stereo digital
audio. The device includes an inherent sam-
ple/hold and an on-chip analog switch for stereo
operation. Both left and right channels can thus
be sampled and converted at rates up to 50kHz
per channel. Alternatively, the CS5126 can be
implemented in 2X oversampling schemes for
improved dynamic range and distortion.
Output data is available in serial form with
either binary or 2’s complement coding. Control
outputs are also supplied for use with an external
sample/hold amplifier to implement simultane-
ous sampling.
THEORY OF OPERATION
The CS5126 implements a standard successive
approximation algorithm using a charge-redistri-
bution architecture. Instead of the traditional re-
sistor network, the DAC is an array of binary-
weighted capacitors. When not converting, the
CS5126 tracks the analog input signal. The input
voltage is applied across each leg of the DAC
capacitor array, thus performing a voltage-to-
charge conversion.
When the conversion command is issued, the
charge is trapped on the capacitor array and the
analog input is thereafter ignored. In effect, the
entire DAC capacitor array serves as analog
memory during conversion much like a hold ca-
pacitor in a sample/hold amplifier.
The conversion consists of manipulating the bi-
nary-weighted legs of the capacitor array to the
voltage reference and analog ground. All legs
share one common node at the input to the con-
verter’s comparator. This forms a binary-
weighted capacitive divider. Since the charge at
the comparator’s input remains fixed, the voltage
at that point depends on the proportion of ca-
pacitance tied to VREF versus AGND. The suc-
DS32F1
cessive-approximation algorithm is used to find
the proportion of capacitance which will drive
the voltage to the comparator’s trip point. That
binary fraction of capacitance represents the con-
verter’s digital output.
Calibration
The ability of the CS5126 to convert accurately
clearly depends on the accuracy of its DAC. The
CS5126 uses an on-chip self-calibration scheme
to insure low distortion and excellent dynamic
range independent of input signal conditions.
Each binary-weighted bit capacitor actually con-
sists of several capacitors which can be manipu-
lated to adjust the overall bit weight. During
calibration, an on-chip microcontroller manipu-
lates the sub-arrays to precisely ratio the bits.
Each bit is adjusted to just balance the sum of
all less significant bits plus one dummy LSB
(for example, 16C = 8C + 4C + 2C + C + C).
The result is typical differential nonlinearity of
3/4 to 5/4 LSB’s wide.
The CS5126 should be reset upon power-up,
thus initiating a calibration cycle which takes 1.4
seconds to complete. The CS5126 then stores its
calibration coefficients in on-chip SRAM, and
can be recalibrated at any later time.
SYSTEM DESIGN WITH THE CS5126
All timing and control inputs to the CS5126 can
be easily generated from a master system clock.
The CS5126 outputs serial data and a variety of
digital outputs which can be used to control an
external sample/hold amplifier for simultaneous
sampling. The actual circuit connections depend
on the system architecture (stereo or monaural
2X oversampling), and on the sampling charac-
teristics (simultaneous or sequential sampling
between channels).
1/4 LSB. That is, codes typically range from
CS5126
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