LPC4310FET100,551 NXP Semiconductors, LPC4310FET100,551 Datasheet - Page 141

• Manufacturer Part Number: LPC4310FET100,551
• Description: IC MCU 32BIT 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4310FET100,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 168K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
17. Revision history
Table 30.
LPC4350_30_20_10
Objective data sheet
Document ID
LPC4350_30_20_10 v.2.1
Modifications:
LPC4350_30_20_10 v.2
LPC4350_30_20_10 v.1
Revision history
Release date Data sheet status
20110923
20110714
20101029
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
Objective data sheet
Objective data sheet
Objective data sheet
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LQFP100 package added in
Pin P2_7 designated as ISP entry pin.
Boot pins corrected in
P2_9 as boot pin. Pin level corrected for 4th boot pin (pin P2_9) in
Table
USART3 boot mode added in
Description of ISP mode added
V
Table 2
Pin description of Pin P2_2 updated: Function CTOUT_6 changed to
CTIN_6.
Pin description of Pin PF_9 updated: Function SGPIO7 changed to
SGPIO3.
LQFP208 package added in
SPIFI memory added in
AHB multilayer matrix connections updated in
Pin P7_2, column LQFP144: replaced 113 by 115 in
I
updated for I/O pins (see
5.
updated.
32-bit ARM Cortex-M4/M0 microcontroller
Table 3
-
Change notice Supersedes
Figure
Table
LPC4350/30/20/10
Table
Table
Table
and
9.
(Section
6).
3.
3.
Table
5.
5: Pin P2_7 replaced by pin
7.11).
LPC4350_30_20_10 v.2
LPC4350_30_20_10 v.1
-
Figure
© NXP B.V. 2011. All rights reserved.
Table
8.
3.
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