LPC4310FET100,551 NXP Semiconductors, LPC4310FET100,551 Datasheet - Page 73
LPC4310FET100,551
Manufacturer Part Number
LPC4310FET100,551
Description
IC MCU 32BIT 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4310FET100,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
168K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4310FET100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.16.1.1 Features
7.16.1 State Configurable Timer (SCT) subsystem
7.16 Configurable digital peripherals
The SCT allows a wide variety of timing, counting, output modulation, and input capture
operations. The inputs and outputs of the SCT are shared with the capture and match
inputs/outputs of the 32-bit general purpose counter/timers.
The SCT can be configured as two 16-bit counters or a unified 32-bit counter. In the
two-counter case, in addition to the counter value the following operational elements are
independent for each half:
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
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Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request (GPIO interrupts).
Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO
group0 and group1 interrupts).
State variable
Limit, halt, stop, and start conditions
Values of Match/Capture registers, plus reload or capture control values
Clock selection
Inputs
Events
Outputs
Interrupts
Two 16-bit counters or one 32-bit counter.
Counter(s) clocked by bus clock or selected input.
Up counter(s) or up-down counter(s).
State variable allows sequencing across multiple counter cycles.
Event combines input or output condition and/or counter match in a specified state.
Events control outputs and interrupts.
Selected event(s) can limit, halt, start, or stop a counter.
Supports:
– 8 inputs (one input connected internally)
– 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2011. All rights reserved.
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