P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 42
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P80C592FFA/00,518
Manufacturer Part Number
P80C592FFA/00,518
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C592FFA00512.pdf
(108 pages)
Specifications of P80C592FFA/00,518
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
13.5.9
The contents of Bus Timing Register 0 defines the values
of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW).
Table 45 Bus Timing Register 0 (address 6)
Table 46 Description of the BTR0 bits
1996 Jun 27
BIT SYMBOL
7
6
5
4
3
2
1
0
8-bit microcontroller with on-chip CAN
SJW.1
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
7
B
US
T
IMING
Synchronization Jump Width. To compensate for phase shifts between clock oscillators of different
bus controllers, any bus controller must resynchronize on any relevant signal edge of the current
transmission. The synchronization jump width defines the maximum number of clock cycles a bit
period may be shortened or lengthened by one resynchronization:
Baud Rate Prescaler. The period of the system clock t
individual bit timing.The system clock is calculated using the following equation:
Where t
t
t
SJW.0
SJW
SCL
R
6
EGISTER
=
=
CLK
2t
t
SCL
CLK
= time period of the P8xC592 oscillator.
0 (BTR0)
2SJW.1
32BRP.5
BRP.5
5
+
˙˙
SJW.0
+
16BRP.4
BRP.4
+
4
1
.
+
8BRP.3
42
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
For further information on bus timing, see
Sections 13.5.10 and 13.5.18.
FUNCTION
BRP.3
+
3
4BRP.2
SCL
+
is programmable and determines the
2BRP.1
BRP.2
2
+
BRP.0
BRP.1
+
1
1
Product specification
.
P8xC592
BRP.0
0