STM32F407VGT6 STMicroelectronics, STM32F407VGT6 Datasheet - Page 19

• Manufacturer Part Number: STM32F407VGT6
• Description: IC MCU 32BIT 1MB FLASH 100LQFP
• Manufacturer: STMicroelectronics

Specifications of STM32F407VGT6

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 168MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: ARM Cortex M4
• Processor Series: STM32F4
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 168 MHz
• Data Ram Size: 192 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 82
• Number Of Timers: 10
• Operating Supply Voltage: 1.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: CAN, I2C, I2S, SPI, UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11605

STM32F405xx, STM32F407xx
Figure 6.
2.2.8
Multi-AHB matrix
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
Doc ID 022152 Rev 1
Description
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