STM32F407VGT6 STMicroelectronics, STM32F407VGT6 Datasheet - Page 24

• Manufacturer Part Number: STM32F407VGT6
• Description: IC MCU 32BIT 1MB FLASH 100LQFP
• Manufacturer: STMicroelectronics

Specifications of STM32F407VGT6

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 168MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: ARM Cortex M4
• Processor Series: STM32F4
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 168 MHz
• Data Ram Size: 192 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 82
• Number Of Timers: 10
• Operating Supply Voltage: 1.7 V to 3.6 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: CAN, I2C, I2S, SPI, UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11605

Description
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Regulator OFF
This mode allows to power the device as soon as V
●
●
Regulator OFF/internal reset ON
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG and PDR_ON pins to V
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
–
In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it
allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the
internal voltage regulator in off.
Regulator OFF/internal reset OFF
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG pin to V
allows to supply externally a 1.2 V voltage source through V
addition to V
The following conditions must be respected:
–
–
–
V
between power domains.
If the time for V
reach 1.8 V
Otherwise, PA0 should be asserted low externally during POR until V
1.8 V (see
If V
must be asserted on PA0 pin.
V
between power domains.
PA0 should be kept low to cover both conditions: until V
1.08 V and until V
NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
DD
CAP_1
should always be higher than V
should always be higher than V
DD
and V
.
Figure
(a)
CAP_1
, then PA0 should be connected to the NRST pin (see
CAP_1
CAP_2
DD
9).
and V
DD
DD
Doc ID 022152 Rev 1
reaches 1.8 V (see
and V
and by applying an inverted reset signal to PDR_ON, and
go below 1.08 V and V
is below 1.8 V (see
CAP_2
CAP_2
pins, in addition to V
to reach 1.08 V is faster than the time for V
DD
CAP_1
CAP_1
.
Figure
DD
and V
and V
Figure
DD
reaches 1.8 V.
8).
is higher than 1.7 V, then a reset
CAP_2
CAP_2
9).
STM32F405xx, STM32F407xx
DD
.
to avoid current injection
to avoid current injection
CAP_1
CAP_1
and V
and V
CAP_2
CAP_2
Figure
DD
reaches
pins, in
reach
8).
DD
to