S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 20

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION (X27A-A-001-06)
Pin Names
RD/WR#
RESET#
WAIT#
BCLK
WE1#
RD#
CS#
BS#
Type
O
I
I
I
I
I
I
I
Pin #
78
74
71
75
79
76
73
2
Table 5-1 Host Interface Pin Descriptions
Cell
TS2
CS
CS
CS
CS
CS
C
C
RESET#
State
Input
Input
Input
Input
Input
Input
Hi-Z
0
EPSON
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the write enable signal for the
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For Generic #1, this pin inputs the write enable signal for the upper
• For Generic #2, this pin inputs the byte enable signal for the high
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
This pin inputs the chip select signal.
This pin inputs the system bus clock.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the bus start signal (BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For Generic #1, this pin must be tied to V
• For Generic #2, this pin must be tied to IO V
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For Generic #1, this pin inputs the read command for the upper
• For Generic #2, this pin must be tied to IO V
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the read signal (RD#).
• For MC68K #1, this pin must be tied to IO V
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
• For Generic #1, this pin inputs the read command for the lower
• For Generic #2, this pin inputs the read command (RD#).
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
This pin has multiple functions.
• For SH-3 mode, this pin outputs the wait request signal (WAIT#).
• For SH-4 mode, this pin outputs the device ready signal (RDY#).
• For MC68K #1, this pin outputs the data transfer acknowledge sig-
• For MC68K #2, this pin outputs the data transfer and size acknowl-
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
See Table 5-7, “Host Bus Interface Pin Mapping,” on page 1-13 for
summary.
Active low input to set all internal registers to the default state and to
force all signals to their inactive states.
upper data byte (WE1#).
data byte (WE1#).
data byte (BHE#).
S1D13705 needs this signal for early decode of the bus cycle.
data byte (RD1#).
data byte (RD0#).
nal (DTACK#).
edge bit 1 (DSACK1#).
Description
SS
.
DD
DD
DD
.
.
.
5: PINS
1-11