S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 235

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

5: INTERFACING TO THE TOSHIBA MIPS TMPR3912 MICROPROCESSOR
IT8368E Configuration
5-34
IT8368E
TMPR3912
LHA[23]/MFIO[10]
LHA[22]/MFIO[9]
LHA[21]/MFIO[8]
LHA[20]/MFIO[7]
LHA[19]/MFIO[6]
LHA[16:13]/
MFIO[3:0]
CARDxWAIT*
Note: See Section , “Host Bus Pin Connection” on page 5-29 and Section , “Generic #1 Interface
The “Generic #1” host interface control signals of the S1D13705 are asynchronous with respect to
the S1D13705 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on pixel and frame rates,
power budget, part count and maximum S1D13705 respective clock frequencies. Also, internal
S1D13705 clock dividers provide additional flexibility.
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E must have both “Fix
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide
control signals needed by the S1D13705 host bus interface, and a 16M byte portion of the system
PC Card attribute and IO space is allocated to address the S1D13705. When accessing the
S1D13705 the associated card-side signals are disabled in order to avoid any conflicts.
For mapping details, refer to section 3.3: “Memory Mapping and Aliasing.” For connection details
see Figure 5-2, “S1D13705 to TMPR3912 Connection Using an IT8368E,” above. For further
information on the IT8368E, refer to the “IT8368E PC Card/GPIO Buffer Chip Specification”.
Note: When a second IT8368E is used, that circuit should not be set in VGA mode.
DCLKOUT
D[31:24]
D[23:16]
A[12:0]
ENDIAN
Mode” on page 5-30 for Generic #1 pin descriptions.
Figure 5-2 S1D13705 to TMPR3912 Connection Using an IT8368E
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
V
DD
Clock divider
pull-up
EPSON
...or...
Oscillator
System RESET
S1D13705F00A APPLICATION NOTES
+3.3V
See text
RESET#
AB[12:0]
AB[16:13]
DB[7:0]
DB[16:8]
WAIT#
BS#
WE1#
WE0#
RD/WR#
RD#
CS#
IO V
CLKI
BCLK
S1D13705
DD
(X27A-G-004-01)
, CORE V
DD