S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 240

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

6.4 Direct Connection to the Philips PR31500/PR31700
General Description
S1D13705F00A APPLICATION NOTES
(X27A-G-012-01)
In this example implementation the S1D13705 occupies the PR31500/PR31700 PC Card slot #1.
The S1D13705 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The
address bus of the PR31500/PR31700 PC Card interface is multiplexed and must be demultiplexed
using an advanced CMOS latch (e.g., 74AHC373). The direct connection approach makes use of the
S1D13705 in its “Generic #2” interface configuration.
The following diagram demonstrates a typical implementation of the interface.
Note: See Section , “Host Bus Pin Connection” on page 5-29 and Section , “Generic #2 Interface
The “Generic #2” host interface control signals of the S1D13705 are asynchronous with respect to
the S1D13705 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
/CARDIOREAD
ENDIAN
PR31500/PR31700
/CARD1WAIT
/CARDIOWR
/CARD1CSH
/CARD1CSL
DCLKOUT
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Mode” on page 5-26 for Generic #2 pin descriptions.
D[31:24]
D[23:16]
A[12:0]
ALE
Figure 6-1 S1D13705 to PR31500/PR31700 Direct Connection
Latch
V
DD
Clock divider
6: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
pull-up
EPSON
...or...
Oscillator
System RESET
+3.3V
+3.3V
+3.3V
See text
BS#
RD/WR#
IO V
RD#
WE0#
WE1#
CLKI
BCLK
CS#
AB[16:13]
AB[12:0]
DB[7:0]
DB[15:8]
WAIT#
RESET#
S1D13705
DD
, CORE V
DD
5-39