S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 253

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

8: INTERFACING TO THE NEC VR4181A
S1D13705 Hardware Configuration
NEC VR4181A Configuration
5-52
CNF2
The host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705
bus clock. This gives the system designer full flexibility to choose the appropriate source (or
sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and whether
an external or internal clock divider is needed, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum S1D13705 clock frequencies.
The S1D13705 also has internal clock dividers providing additional flexibility.
The S1D13705 uses CNF3 through CNF0 and BS# to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. Refer to the “S1D13705 Hardware Functional
Specification”, document number X27A-A-001-02 for details.
The tables below show those configuration settings important to the Generic #2 host bus interface.
The NEC VR4181A must be configured through its internal registers in order to map the S1D13705
to the external LCD controller space. The following register values must be set.
Register LCDGPMD at address 0B00 032Eh must be set as follows.
• Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD
• Bits [1:0] must be set to 01b to reserve 128Kbytes of memory address range
Register GPMD2REG at address 0B00 0304h must be set as follows.
• Bits [9:8] (GP20MD[1:0]) must be set to 11b to map pin GPIO20 to #UBE.
• Bits [5:4] (GP18MD[1:0]) must be set to 01b to map pin GPIO18 to IORDY.
CNF1
CNF0
CNF2
CNF3
1
controller interface. This also maps pin SHCLK to #LCDCS and pin LOCLK to #MEMCS16.
133E 0000h to 133F FFFFh for the external LCD controller.
Signal
= configuration for NEC VR4181A support
See “Host Bus Interface Selection” table8-3
below.
Little Endian
= configuration for NEC VR4181A support
CNF1
1
value on this pin at the rising edge of RESET# is used to configure: (0/1)
Table 8-2 Summary of Power-On/Reset Options
Table 8-3 Host Bus Interface Selection
0
CNF0
TM
1
MICROPROCESSOR
EPSON
BS#
1
See “Host Bus Interface Selection” table8-3 below.
Big Endian
S1D13705F00A APPLICATION NOTES
Host Bus Interface
Generic #2, 16-bit
1
(X27A-G-013-01)