S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 214

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

2.4 MPC821 to S1D13705 Interface
Hardware Description
S1D13705F00A APPLICATION NOTES
(X27A-G-010-01)
The interface between the S1D13705 and the MPC821 requires minimal glue logic. One inverter is
required to change the polarity of the WAIT# signal (an active low signal) to insert wait states in the
bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an active low signal which ends the
current bus cycle. The inverter is enabled using CS# so that TA is not driven by the S1D13705
during non-S1D13705 bus cycles. A single resistor is used to speed up the rise time of the WAIT#
(TA) signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to GND).
The following diagram shows a typical implementation of the MPC821 to S1D13705 interface.
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
MPC821
Figure 2-3 Typical Implementation of MPC821 to S1D13705 Interface
A[15:31]
SYSCLK
D[0:15]
TA
WE0
WE1
CS4
OE
Vcc
2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
470
System RESET
EPSON
BUSCLK
RESET#
RD/WR#
AB[16:0]
BS#
DB[15:0]
CS#
RD#
WE1#
WAIT#
S1D13705
WE0#
5-13