S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 226

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

Memory Access Cycles
S1D13705F00A APPLICATION NOTES
(X27A-G-009-01)
A[25:0]
A[25:0]
D[15:0]
REG#
REG#
D[15:0]
WAIT#
WAIT#
CE1#
CE2#
OE#
CE1#
CE2#
OE#
WE#
A data transfer is initiated when the memory address is placed on the PC Card bus and one, or both,
of the card enable signals (CE1# and CE2#) are driven low. REG# must be kept inactive. If only
CE1# is driven low, 8-bit data transfers are enabled and A0 specifies whether the even or odd data
byte appears on data bus lines D[7:0]. If both CE1# and CE2# are driven low, a 16-bit word transfer
takes place. If only CE2# is driven low, an odd byte transfer occurs on data lines D[15:8].
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE#
high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT#
low for the time needed to complete the cycle.
Figure 4-1 and Figure 4-2 illustrate typical memory access cycles on the PC Card bus.
Transfer Start
Transfer Start
Hi-Z
Hi-Z
Figure 4-1 PC Card Read Cycle
Figure 4-2 PC Card Write Cycle
EPSON
ADDRESS VALID
ADDRESS VALID
DATA VALID
4: INTERFACING TO THE PC CARD BUS
DATA VALID
Transfer Complete
Transfer Complete
Hi-Z
Hi-Z
5-25