S1D13705F00A200 Epson, S1D13705F00A200 Datasheet - Page 228

• Manufacturer Part Number: S1D13705F00A200
• Manufacturer: Epson

Specifications of S1D13705F00A200

• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

4.4 PC Card to S1D13705 Interface
Hardware Connections
S1D13705F00A APPLICATION NOTES
(X27A-G-009-01)
Note:
When connecting the S1D13705 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13705 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
• WAIT# is a signal which is output from the S1D13705 to the host CPU that indicates when data is
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus interface for
The S1D13705 is interfaced to the PC Card bus with a minimal amount of glue logic. In this
implementation, the address inputs (AB[16:0]) and data bus (DB[15:0] connect directly to the CPU
address (A[16:0]) and data bus (D[15:0]).
The PC Card interface does not provide a bus clock, so one must be supplied for the S1D13705.
Since the bus clock frequency is not critical, nor does it have to be synchronous to the bus signals, it
may be the same as CLKI.
BS# (bus start) is not used by Generic #2 mode but is used to configure the S1D13705 for either
Generic #1 or Generic #2 bus and should be tied high (connected to IO V
RD/WR# is also not used by Generic #2 bus and should be tied high (connected to IO V
The following diagram shows a typical implementation of the PC Card to S1D13705 interface.
PC Card socket
ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the
S1D13705 may occur asynchronously to the display update, it is possible that contention may
occur in accessing the S1D13705 internal registers and/or refresh memory. The WAIT# line
resolves these contentions by forcing the host to wait until the resource arbitration is complete.
This signal is active low and may need to be inverted if the host CPU wait state signal is active
high.
Generic #2 mode. However, BS# is used to configure the S1D13705 for Generic #2 mode and
should be tied high (connected to IO V
A[16:0]
D[15:0]
RESET
WAIT#
CE1#
CE2#
WE#
OE#
Figure 4-3 Typical Implementation of PC Card to S1D13705 Interface
15K pull-up
DD
EPSON
). RD/WR# should also be tied high.
Oscillator
4: INTERFACING TO THE PC CARD BUS
IO V
IO V
DD
DD
DD
).
RD/WR#
BS#
RESET#
AB[16:0]
DB[15:0]
WAIT#
CLKI
RD#
WE0#
WE1#
BUSCLK
CS#
S1D13705
DD
).
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