STEVAL-IPE012V1 STMicroelectronics, STEVAL-IPE012V1 Datasheet - Page 32

• Manufacturer Part Number: STEVAL-IPE012V1
• Description: EVAL BOARD ENERGY METER
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-IPE012V1

• Design Resources: STEVAL-IPE012V1 Schematic STEVAL-IPE012V1 BOM
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: STPM10BTR, STM8L152
• Primary Attributes: Single Phase with 1 Current Transformer & Shunt
• Secondary Attributes: Tamper Detection
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11462

Theory of operation
7.20
Figure 22. Timing for providing remote reset request
1. All time intervals must be longer than 30 ns. t
32/51
Any pin above has an internal weak pull-up mechanism of nominal 15 µA. This means that
when a pin is not forced by external signals, the state of the pin is logic high. A high state of
any input pin described above is considered an idle (not active) state. For the SPI to operate
correctly, the STPM10 must be correctly supplied as described in
An idle state of the SPI module is recognized when the signals of pins SYN, SCS, SCL and
SDA are in a logic high state. Any SPI operation should start from this idle state.
When SCS is active (low), signal SDATD should change its state at trailing edge of signal
SCLNLC and the signal SDATD should be stable at next leading edge of signal SCLNLC.
The first valid bit of SDATD is always started with activation of signal SCLNLC.
Remote reset
The timing diagram of this operation is shown in
30 ns.
The internal reset signal is called RRR. Unlike the POR, the RRR signal does not cause the
30 ms delayed restart of the analog module, and the 120 ms delay in the restart of the digital
module. This signal does not clear the mode signals.
–
SYN
SYN
SCLNLC
SCLNLC
SDATD
SDATD
SCS
SCS
clock signal. When SCS is high, SCL is also high, determining the idle state of the
SPI.
SDA: the data pin. If SCS is low, the operation of SDA is dependent on the status
of the SYN pin. If SYN is high, SDA is the output of the serial bit data (read mode).
If SYN is low, SDA is the input of the serial bit data signal (write mode). If SCS is
high, SDA is the input of the idle signal.
7
→ t
t
1
Doc ID 17728 Rev 3
8
is the reset time; this interval must be longer than 30 ns also.
t
2
t
3
t
4
t
5
t
(1)
6
Figure 22
t
7
. The time step can be as short as
t
8
t
9
Section 7.6: Power supply
t
10
STPM10
.