STEVAL-IPE012V1 STMicroelectronics, STEVAL-IPE012V1 Datasheet - Page 34

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STEVAL-IPE012V1

Manufacturer Part Number
STEVAL-IPE012V1
Description
EVAL BOARD ENERGY METER
Manufacturer
STMicroelectronics
Series
-r

Specifications of STEVAL-IPE012V1

Design Resources
STEVAL-IPE012V1 Schematic STEVAL-IPE012V1 BOM
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
STPM10BTR, STM8L152
Primary Attributes
Single Phase with 1 Current Transformer & Shunt
Secondary Attributes
Tamper Detection
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11462
Theory of operation
Figure 24. Timing for data record reading
7.22
34/51
SCS
SCS
SYN
SYN
SCLNLC
SCLNLC
SDATD
SDATD
The system that reads the data record from the STPM10 should check the integrity of each
data record. If the check fails, the reading should be repeated, but this time only the shifting
should be applied. Otherwise, new data would be latched into transmission latches and the
one incorrectly read would be lost.
Normally, each byte is read out as the most significant bit (MSB) first. But this can be
changed by setting the MSBF configuration bit in the STPM10 CFL data record. If this is
done, each byte is read out as the least significant bit (LSB) first.
Writing procedure
Each writable bit (configuration and mode bits) has its own 6-bit absolute address. For the
configuration bits, the 6-bit address value corresponds to its decimal value, while for the
mode bits the addresses are the ones indicated in
In order to change the state of a latch, one must send a byte of data to the STPM10, which
is the normal way to send data via SPI. This byte consists of 1-bit data to be latched (MSB),
followed by the 6-bit address of the destination latch, followed by 1-bit don't care data (LSB),
which makes a total of 8 bits of command byte.
For example, if we want to set configuration bit 47 (part of the secondary current channel
calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111. The byte
command is then composed as follows:
t
1
t
2
t
t
t
t
t
t
t
1
2
3
4
5
7
8
: Internal data transferred to SDA
: SDA data is stable and can be read
→ t
→ t
→ t
→ t
→ t
2
3
4
5
6
: Latching phase. Interval value > 2/f
: Data latched, SPI idle. Interval value > 30 ns
: Enable SPI for read operation. Interval value > 30 ns
: Serial clock counter is reset. Interval value > 30 ns
: SPI reset and enabled for read operation. Interval value > 30 ns
t
3
t
4
t
5
t
6
Doc ID 17728 Rev 3
t
7
t
8
1st byte
1st byte
f(read)
f(read)
Section 7.18: Mode signals
CLK
last bit of 32nd byte
last bit of 32nd byte
.
STPM10

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