ED DDR3 1G PCF8000 Samsung Semiconductor, ED DDR3 1G PCF8000 Datasheet - Page 3

• Manufacturer Part Number: ED DDR3 1G PCF8000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCF8000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 130mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
Table Contents
1.0 Ordering Information .................................................................................................................. 5
2.0 Key Features ................................................................................................................................ 5
3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6
4.0 Input/Output Functional Description ....................................................................................... 11
5.0 DDR3 SDRAM Addressing ........................................................................................................ 12
6.0 Absolute Maximum Ratings ...................................................................................................... 13
7.0 AC & DC Operating Conditions ................................................................................................ 13
8.0 AC & DC Input Measurement Levels ........................................................................................ 14
9.0 AC & DC Output Measurement Levels ..................................................................................... 19
10.0 IDD Specification Parameters and Test Conditions ............................................................. 29
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package
3.3 x16 Package Pinout (Top view) : 96ball FBGA Package
3.4 FBGA Package Dimension (x4/x8)
3.5 FBGA Package Dimension (x16)
6.1 Absolute Maximum DC Ratings
6.2 DRAM Component Operating Temperature Range
7.1 Recommended DC operating Conditions (SSTL_1.5)
8.1 AC & DC Logic input levels for single-ended signals
8.2 V
8.3 AC & DC Logic Input Levels for Differential Signals
8.4 Differential Input Cross Point Voltage
8.5 Slew rate definition for Differential Input Signals
8.6 Slew rate definition for Differential Input Signals
9.1 Single-ended AC & DC Output Levels
9.2 Differential AC & DC Output Levels
9.3 Single-ended Output Slew Rate
9.4 Differential Output Slew Rate
9.5 Reference Load for AC Timing and Output Slew Rate
9.6 Overshoot/Undershoot Specification
9.7 34ohm Output Driver DC Electrical Characteristics
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
9.9 ODT Timing Definitions
10.1 IDD Measurement Conditions
8.3.1 Differential signals definition
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
8.3.3 Single-ended requirements for differential signals
9.6.1 Address and Control Overshoot and Undershoot specifications
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
9.7.1 Output Drive Temperature and Voltage Sensitivity
9.8.1 ODT DC Electrical Characteristics
9.8.2 ODT Temperature and Voltage sensitivity
9.9.1 Test Load for ODT Timings
9.9.2 ODT Timing Definitions
REF
Tolerances
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1Gb DDR3 SDRAM
Rev. 1.0 February 2009
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