SI3063-F-FS Silicon Laboratories Inc, SI3063-F-FS Datasheet - Page 17

• Manufacturer Part Number: SI3063-F-FS
• Description: IC DAA ENH GLOB LINE-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Type: Integrated Direct Access Arrangementr

Specifications of SI3063-F-FS

• Package / Case: *
• Function: Direct Access Arrangement (DAA)
• Number Of Circuits: 1
• Current - Supply: 9mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Billing Tone Detection, Line Voltage Monitor, Loop Current Monitor, Overload Detection, Ring Detector
• Supply Current: 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Power (watts): -
• Interface: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.6. Calibration
The DAA initiates two auto-calibrations by default when
the device goes off-hook or experiences a loss in line
power. A 17 ms resistor calibration is performed to allow
circuitry internal to the DAA to adjust to the exact line
conditions present at that time. This resistor calibration
can be disabled by setting the RCALD bit (Register 25,
bit 5). A 256 ms ADC calibration is also performed to
remove offsets that might be present in the on-chip A/D
converter which could affect the A/D dynamic range.
The ADC auto-calibration is initiated after the DAA dc
termination stabilizes, and the resistor calibration
completes. Because large variations in line conditions
and line card behavior exist, it could be beneficial to use
manual calibration instead of auto-calibration.
Execute manual ADC calibration as close as possible to
256 ms before valid transmit/receive data is expected.
Take the following steps to implement manual ADC
calibration:
1. The CALD (auto-calibration disable—Register 17) bit
2. The MCAL (manual calibration) bit must be toggled
3. The calibration is completed in 256 ms.
6.7. In-Circuit Testing
With the Si306x’s advanced design the designer can
determine system functionality during production line
tests, and during support for end-user diagnostics. Two
loopback modes allow increased coverage of system
components. Four of the test modes require a line-side
power source. Although a standard phone line can be
used, the test circuit in Figure 1 on page 5 is adequate.
In addition, an off-hook sequence must be performed to
connect the power source to the line-side device.
For the start-up test mode, line-side power is not
necessary and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line-
side is in a powerdown mode and the DSP-side is in a
digital loop-back mode. Data received on SDI passes
through the internal filters and transmitted on SDO
which introduces approximately 0.9 dB of attenuation
on the SDI signal received. The group delay of both
transmit and receive filters exists between SDI and
SDO. Clearing the PDL bit disables this mode and the
SDO data is switched to the receive data from the line-
side. When the PDL bit is cleared, the FDT bit
(Register 12, bit 6) becomes active, indicating the
successful communication between the line-side and
DSP-side. This can be used to verify that the
must be set to 1.
to 1 and then 0 to begin and complete the
calibration.
Rev. 0.9
communications link is operational.
The digital data loop-back mode offers a way to input
data on the SDI pin and have the identical data output
on the SDO pin (but bypassing the transmit and receive
filters). Setting the DDL bit (Register 10, bit 0) enables
this mode. No line-side power or off-hook sequence is
required for this mode, which provides an easy way to
verify communication between the host processor and
the DAA.
The remaining test modes require an off-hook sequence
to operate. The following sequence defines the off-hook
requirements:
1. Powerup or reset.
2. Program the clock generator to the chosen sample
3. Enable line-side by clearing the PDL bit.
4. Issue an off-hook command.
5. Delay 402.75 ms to allow calibration to occur.
6. Set the test mode.
In the isolation digital loopback mode, the host sends a
digital input test pattern on SDI and receives that digital
test pattern back on SDO. To enable this mode, set the
IDL bit (Register 1, bit 1). In this mode, the isolation
barrier is tested. The digital stream is delivered across
the isolation capacitors, C1 and C2 of the "3. Typical
Application Schematic" on page 9, to the line-side
device and returned across the same barrier. In this
mode, the 0.9 dB attenuation and filter group delays
also exist.
The analog loopback mode allows an external device to
drive a signal on the telephone line into the line-side
device and returns the signal on to the line. This mode
allows testing of external components connecting the
RJ-11 jack (TIP and RING) to the line-side device. To
enable this mode, set the AL bit (Register 2).
The PCM analog loopback mode extends the signal
path of the analog loopback mode. In this mode, an
analog signal can be driven from the line into the Si3019
line-side device. This analog signal is converted to
digital data and then passed across the isolation barrier
capacitors to the system-side device. The data passes
through the receive filter, is routed back through the
transmit filter, and is then passed back across the
isolation barrier and sent back out onto the line as an
analog signal. Set the PCML bit (Register 33, bit 7) to
enable this mode.
The final testing mode, internal analog loopback, allows
the system to test the basic operation of the transmit
and receive paths on the line-side device and the
external
Application Schematic" on page 9. In this test mode, the
rate.
components
shown
in
the
Si306x
"3.
Typical
17