DS21Q50L Maxim Integrated Products, DS21Q50L Datasheet - Page 24

• Manufacturer Part Number: DS21Q50L
• Description: IC TRANSCEIVER E1 QUAD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q50L

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

4. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21Q50 is configured through a set of seven control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the device has been
initialized, the control registers only need to be accessed when there is a change in the system
configuration. There is one receive control register (RCR), one transmit control register (TCR), and five
common control registers (CCR1 to CCR5). Each of these registers is described in this section.
There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed
to 1, indicating that an E1 quad transceiver is present. The next three MSBs are reserved for future use.
The lower 4 bits of the device ID register are used to identify the revision of the device. This register
exists in Transceiver 1 only (TS0, TS1 = 0).
The test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On
power-up, the test registers should be set to 00h in order for the DS21Q50 to operate properly.
Register Name:
Register Description:
Register Address:
Bit
Name
Note 1:
Note 2:
ADDRESS
BIT
7
6
5
4
3
1
2
0
2C
2D
2E
2F
The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0).
Only the factory uses the test registers; these registers must be cleared (set to all zeros) on power-up initialization to
ensure proper operation.
NAME
ID3
ID2
ID1
ID0
7
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Chip Revision Bit 3. MSB of a decimal code that represents the chip revision.
Chip Revision Bit 2
Chip Revision Bit 1
Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
IDR
Device Identification Register
0F Hex
6
0
TEST1 (set to 00h)
NAME
PCLB2
PCLB3
PCLB4
5
0
4
0
Per-Channel Loopback Control 2
Per-Channel Loopback Control 3
Per-Channel Loopback Control 4
Test 1 (Note 2)
24 of 87
FUNCTION
ID3
3
FUNCTION
ID2
2
ID1
1
ID0
0