DS21Q50L Maxim Integrated Products, DS21Q50L Datasheet - Page 34

• Manufacturer Part Number: DS21Q50L
• Description: IC TRANSCEIVER E1 QUAD 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q50L

• Function: Transceiver
• Interface: E1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 230mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: AIS Alarms Detector and Generator, Loopback Functions, PRBS Generator / Detector, Remote Detector and Generator
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit
Name
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is
cleared when the framer has successfully obtained synchronization at the CRC4 level. Disabling the
CRC4 mode (CCR1.0 = 0) can also clear the counter. This counter determines the time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the
CRC4 level cannot be obtained within 400ms, the search should be abandoned and proper action taken.
The CRC4 sync counter rolls over.
Table 5-1. Alarm Criteria
(receive carrier loss)
multiframe alarm)
(receive signaling
(receive unframed
(receive signaling
CRC4SA
(receive remote
CASSA
(receive distant
FASSA
NAME
CSC5
CSC4
CSC3
CSC2
CSC0
ALARM
all zeros)
all ones)
all ones)
RDMA
RUA1
alarm)
RSA1
RSA0
RRA
RCL
CSC5
7
BIT
7
6
5
4
3
2
1
0
Over 16 consecutive frames (one
full MF) time slot 16 contains
fewer than three 0s
Over 16 consecutive frames (one
full MF) time slot 16 contains all
0s
Bit 6 in time slot 16 of frame 0 set
to one for two consecutive MF
Fewer than three 0s in two frames
(512 bits)
Bit 3 of nonalign frame set to 1 for
three consecutive occasions
255 (or 2048) consecutive 0s
received
CSC4
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4
CRC4 Sync Counter Bit 3
CRC4 Sync Counter Bit 2
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter Bit 1 is not accessible.
FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment
word.
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF
alignment word.
SSR
Synchronizer Status Register
09 Hex
6
SET CRITERIA
CSC3
5
CSC2
4
34 of 87
CSC0
Over 16 consecutive frames (one full
MF) time slot 16 contains three or
more 0s
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single 1
Bit 6 in time slot 16 of frame 0 set to 0
for two consecutive MF
More than two 0s in two frames (512
bits)
Bit 3 of nonalign frame set to 0 for
three consecutive occasions
In 255-bit times, at least 32 1s are
received
FUNCTION
3
CLEAR CRITERIA
FASSA
2
CASSA
1
CRC4SA
0
ITU SPEC
1.6.1.2
G.775/
G.732
G.732
O.162
O.162
O.162
G.962
2.1.5
2.1.4
4.2
5.2