AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 198
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 198 of 1012
- Download datasheet (16Mb)
15.6.6.2
Figure 15-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
15.6.6.3
32072G–11/2011
A[AD_MSB:2]
CLK_SMC
D[15:0]
NCS0
NWE
NRD
TDF optimization disabled (MODE.TDFMODE = 0)
TDF optimization enabled (MODE.TDFMODE = 1)
Read access on NCS0 (NRD controlled)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 15-21 on page 198
controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float period is ended when the second access begins. If the hold period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 15-22 on page
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
NRDHOLD = 4
199,
TDFCYCLES = 6
shows a read access controlled by NRD, followed by a write access
Figure 15-23 on page 199
Read to Write
Wait State
NWESETUP = 3
Write access on NCS0 (NWE controlled)
and
Figure 15-24 on page 200
illustrate
198
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