AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 632
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 632 of 1012
- Download datasheet (16Mb)
26.7.2
26.7.2.1
26.7.2.2
26.7.2.3
32072G–11/2011
USB Device Operation
Introduction
USB reset
Power-On and reset
In device mode, the USBB supports hi- full- and low-speed data transfers.
In addition to the default control endpoint, seven endpoints are provided, which can be config-
ured with the types isochronous, bulk or interrupt, as described in
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
Figure 26-12 on page 632
Figure 26-12. Device Mode States
After a hardware reset, the USBB device mode is in the Reset state. In this state:
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
• All the endpoints are disabled, except the default control endpoint.
one).
describes the USBB device mode main states.
RESET
HW
| ID = 0
USBE = 0
“Device mode”
Reset
| ID = 0
& ID = 1
USBE = 0
state>
other
<any
USBE = 1
for further details.
Idle
.Table 26-1 on page
617.
632
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