AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 821

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
The command ALL_SEND_CID and the fields and values for CMDR register are described in
Table 30-5 on page 821
Table 30-5.
Note:
Table 30-6.
The Argument Register (ARGR) contains the argument field of the command.
To send a command, the user must perform the following steps:
The command is sent immediately after writing the command register.
As soon as the command register is written, then the Command Ready bit in the Status Register
(SR.CMDRDY) is cleared.
It is released and the end of the card response.
If the command requires a response, it can be read in the Response Registers (RSPRn). The
response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds
an error detection to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if
needed. In this example, the status register bits are polled but setting the appropriate bits in the
Interrupt Enable Register (IER) allows using an interrupt method.
CMD Index
CMD2
Field
CMDNB (command number)
RSPTYP (response type)
SPCMD (special command)
OPCMD (open drain command)
MAXLAT (max latency for command to
response)
TRCMD (transfer command)
TRDIR (transfer direction)
TRTYP (transfer type)
IOSPCMD (SDIO special command)
• Set the ARGR register with the command argument.
• Set the CMDR register (see
bcr means broadcast command with response.
ALL_SEND_CID Command Description
Fields and Values for the CMDR register
Type
bcr
Argument
[31:0] stuff bits
and
Table 30-6 on page
Table 30-6 on page
Resp
R2
Value
2 (CMD2)
2 (R2: 136 bits response)
0 (not a special command)
1
0 (NID cycles ==> 5 cycles)
0 (No transfer)
X (available only in transfer command)
X (available only in transfer command)
0 (not a special command)
Abbreviation
ALL_SEND_CID
821.
821).
Command
Description
Asks all cards to
send their CID
numbers on the
CMD line
821