AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 343

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Note:
Note:
Note:
3. Write the starting destination address in the DARx register for channel x.
4. Write the channel configuration information into the CFGx register for channel x.
5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
7. Make sure that the LLI.SARx register location of all LLIs in memory point to the start
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
10. Program the CTLx, CFGx registers according to Row 8 as shown in
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
14. Source and destination requests single and burst DMACA transactions to transfer the
15. The DMACA does not wait for the block interrupt to be cleared, but continues and
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
shown in Row 8 of
Linked List item must be set as described in Row 1 or Row 5 of
326.
are non-zero and point to the next Linked List Item.
source block address proceeding that LLI fetch.
memory is cleared.
a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
page 326
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
block of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transaction (burst and single) in the block and carry out the block
transfer.
fetches the next LLI from the memory location pointed to by current LLPx register and
automatically reprograms the SARx, CTLx and LLPx channel registers. The DARx reg-
ister is left unchanged. The DMA transfer continues until the DMACA samples the
CTLx and LLPx registers at the end of a block transfer match that described in Row 1
The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although
fetched during an LLI fetch, are not used.
The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. The LLI.DARx register
location of the LLI although fetched is not used. The DARx register in the DMACA remains
unchanged.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DEST_PER bits, respectively.
Figure 19-7 on page 325
Table 19-1 on page
shows a Linked List example with two list items.
326, while the LLI.CTLx register of the last
Table 19-1 on page
Table 19-1 on
343