AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 575
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 575 of 1012
- Download datasheet (16Mb)
Figure 25-40. Header Reception
25.6.9.7
Figure 25-42. Slave Node Synchronization
32072G–11/2011
With RSTSTA=1
Fractional Part (FP)
Clcok Divider (CD)
Write US_CR
Synchro Counter
Baud Rate
US_LINIR
Baud Rate
Clock
LINID
LINIDRX
RXD
BRGR
BRGR
Clock
RXD
Slave Node Synchronization
Synchronization is only done by the slave. If the Sync field is not 0x55, an Inconsistent Sync
Field error (CSR.LINISFE) is generated. The time between falling edges is measured by a 19-bit
counter, driven by the sampling clock (see
Figure 25-41. Sync Field
The counter starts when the Sync field start bit is detected, and continues for eight bit periods.
The 16 most significant bits (counter value divided by 8) becomes the new clock divider
(BRGR.CD), and the three least significant bits (the remainder) becomes the new fractional part
(BRGR.FP).
The synchronization accuracy depends on:
13 dominant bits (at 0)
• The theoretical slave node clock frequency; nominal clock frequency (F
• The baud rate
Break Field
13 dominant bits (at 0)
Break Field
Initial CD
1 recessive bit
Initial FP
Start
Delimiter
Break
bit
(at 1)
2 Tbit
1 recessive bit
Delimiter
Break
(at 1)
Start
Bit
Reset
1
Start
Bit
2 Tbit
0
1
Synch Byte = 0x55
1
0
8 Tbit
0
Synch Byte = 0x55
Section
1
Synch Field
1
0
0
2 Tbit
1
1
25.6.1).
0
0
1
Stop
Bit
0
Start
Bit
000_0011_0001_0110_1101
2 Tbit
Stop
Bit
ID0 ID1 ID2
0000_0110_0010_1101
101
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
ID3
ID4
Stop
bit
ID5
Nom
ID6
)
ID7
Stop
Bit
Stop
Bit
575
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