AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 650
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 650 of 1012
- Download datasheet (16Mb)
32072G–11/2011
TXOUTI
FIFOCON
The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-
CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data
Interrupt Enable (TXOUTE) bit in UPCONn is one.
TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the
pipe FIFO.
The user then writes into the FIFO (see
DATA)” on page
OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.
Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.
Note that in High-Speed operating mode, the host controller automatically manages the PING
protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the
Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction
(BINTERVALL) field in UPCFGn. See the
Figure 26-26. Example of an OUT Pipe with one Data Bank
SW
write data to CPU
BANK 0
740) and clears the FIFOCON bit to allow the USBB to send the data. If the
SW
OUT
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
Section 26.8.3.12
(bank 0)
DATA
HW
ACK
for more details.
SW
write data to CPU
BANK 0
SW
OUT
650
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