AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 157

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.6
16.6.1
Table 16-1.
16.6.2
Table 16-2.
Note:
32059L–AVR32–01/2012
0x00C
0x01C
0x02C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
(0x000 - 0x03F)+m*0x040
User Interface
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Offset
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
+ n*0x040
Address Range
0x000 - 0x03F
0x040 - 0x07F
Memory Map Overview
Channel Memory Map
PDCA Register Memory Map
PDCA Channel Configuration Registers
...
The channels are mapped as shown in
isters, shown in
Note:
Memory Address Reload Register
Transfer Counter Reload Register
Memory Address Register
Peripheral Select Register
Transfer Counter Register
Interrupt Disable Register
Interrupt Enable Register
Interrupt Status Register
Interrupt Mask Register
1. The reset values are device specific. Please refer to the Module Configuration section at the
Control Register
Status Register
Mode Register
end of this chapter.
Register
Table
16-2, where n is the channel number.
DMA channel m configuration registers
DMA channel 0 configuration registers
DMA channel 1 configuration registers
Table
Register Name
MARR
TCRR
16-1. Each channel has a set of configuration reg-
MAR
PSR
TCR
IDR
IMR
IER
ISR
MR
Contents
CR
SR
...
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
(1)
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