AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 197

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 18-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 18-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
32059L–AVR32–01/2012
SPCK cycle (for reference)
SPCK cycle (for reference)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
SPCK
SPCK
MOSI
MISO
(to slave)
NSS
SPCK
SPCK
MOSI
MISO
NSS
the NCPHA bit. These two parameters determine the edges of the clock signal on which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possi-
ble combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 18-2
Table 18-2.
Figure 18-3 on page 197
***
1
MSB
MSB
MSB
1
shows the four modes and corresponding parameter settings.
MSB
*** Not Defined, but normaly MSB of previous character received
SPI modes
2
6
6
2
SPI Mode
6
6
3
0
1
2
3
5
5
and
3
5
5
Figure 18-4 on page 197
4
4
4
4
4
4
5
3
3
5
3
3
6
2
2
6
2
2
show examples of data transfers.
7
1
1
CPOL
7
0
0
1
1
1
1
8
LSB
8
LSB
LSB
LSB
***
NCPHA
1
0
1
0
197