AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 45

• Manufacturer Part Number: AT32UC3B1128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B1128

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.5.8.4
9.5.9
9.5.10
9.5.11
32059L–AVR32–01/2012
Divided PB clocks
Debug operation
Reset Controller
Generic clock implementation
In AT32UC3B, there are 5 generic clocks. These are allocated to different functions as shown in
Table
Table 9-2.
The clock generator in the Power Manager provides divided PBA and PBB clocks for use by
peripherals that require a prescaled PBx clock. This is described in the documentation for the
relevant modules.
The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx
clocks are stopped.
During a debug session, the user may need to halt the system to inspect memory and CPU reg-
isters. The clocks normally keep running during this debug operation, but some peripherals may
require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program
to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx
clocks. This is described in the documentation for the relevant modules. The divided PBx clocks
are always debug qualified clocks.
Debug qualified PB clocks are stopped during debug operation. The debug system can option-
ally keep these clocks running during the debug operation. This is described in the
documentation for the On-Chip Debug system.
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the need for external reset circuitry to guarantee stable operation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated.
reset sources supported by the Reset Controller.
Clock number
9-2.
0
1
2
3
4
Generic clock allocation
Function
GCLK0 pin
GCLK1 pin
GCLK2 pin
USBB
ABDAC
Table 9-4
lists these and other
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