AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 144
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
- Current page: 144 of 1313
- Download datasheet (20Mb)
9.6.3
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
• PERn: Periodic n
• ALARMn: Alarm n
• OVF: Overflow
32117C–AVR-08/11
CLKREADY: Clock ready
CLKBUSY: Clock busy
READY: AST ready
BUSY: AST busy
31
23
15
7
-
-
-
-
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.CLKBUSY bit has a 1-to-0 transition.
• 0: The clock is ready and can be changed.
• 1: CLOCK.CEN has been written and the clock is busy.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the SR.BUSY bit has a 1-to-0 transition.
0: The AST accepts writes to CR, CV, SCR, WER, EVE, EVD, ARn, and PIRn, and DTR.
1: The AST is busy and will discard writes to CR, CV, SCR, WER, EVE, EVD, ARn, and PIRn, and DTR.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the selected bit in the prescaler has a 0-to-1 transition.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the counter reaches the selected alarm value.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overflow has occurred.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x08
0x00000000
CLKREADY
29
21
13
5
-
-
-
CLKBUSY
28
20
12
4
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
ALARM1
READY
PER1
25
17
9
1
-
AT32UC3C
ALARM0
BUSY
PER0
OVF
24
16
8
0
144
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