AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 507
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
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24.7.1
Name:
Access Type:
Offset:
Reset Value:
• TZQ: Transmit Zero Quantum Pause Frame
• TPF: Transmit Pause Frame
• THALT: Transmit Halt
• TSTART: Start Transmission
• BP: Back Pressure
• WESTAT: Write Enable for Statistics Registers
• INCSTAT: Increment Statistics Registers
• CLRSTAT: Clear ¨Statistics Registers
• MPE: Management Port Enable
• TE: Transmit Enable
32117C–AVR-08/11
WESTAT
31
23
15
7
-
-
-
Writing a one to this bit sends a pause frame with zero pause quantum at the next available transmitter idle time.
Writing a one to this bit sends a pause frame with the pause quantum from the transmit pause quantum register at the next
available transmitter idle time.
Writing a one to this bit halts transmission as soon as any ongoing frame transmission ends.
Writing a one to this bit starts transmission.
0: No collision are forced.
1: In half duplex mode, forces collisions on all received frames.
0: Statistics registers are read-only.
1: Statistics registers are writable for functional test purposes.
Writing a one increments all the statistics registers by one for test purposes.
Writing a one clears the statistics registers.
0: Forces MDIO to high impedance state and DPC low.
1: Enables the management port.
0: Transmission stops immediately, the transmit FIFO and control registers are cleared and the transmit queue pointer register
resets to point to the start of the transmit descriptor list.
1: Enables the Ethernet transmitter to send data.
Network Control Register
INCSTAT
30
22
14
6
-
-
-
NCR
Read/Write
0x00
0x00000000
CLRSTAT
29
21
13
5
-
-
-
MPE
TZQ
28
20
12
4
-
-
TPF
TE
27
19
11
3
-
-
THALT
RE
26
18
10
2
-
-
TSTART
LLB
25
17
9
1
-
-
AT32UC3C
BP
24
16
LB
8
0
-
-
507
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