AT32UC3C0512CAU Atmel Corporation, AT32UC3C0512CAU Datasheet - Page 85
AT32UC3C0512CAU
Manufacturer Part Number
AT32UC3C0512CAU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3A0128AU.pdf
(2 pages)
4.AT32UC3C0128C.pdf
(1313 pages)
5.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0512CAU
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128AU PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- AT32UC3C0128C PDF datasheet #5
- Current page: 85 of 1313
- Download datasheet (20Mb)
8.5.4.1
8.5.4.2
8.5.4.3
8.5.4.4
32117C–AVR-08/11
Enabling a generic clock
Disabling a generic clock
Changing clock frequency
Generic clock implementation
OSCSEL
Figure 8-3.
A generic clock is enabled by writing a one to the CEN bit in GCCTRL to one. Each generic clock
can individually select a clock source by setting the OSCSEL bits. The source clock can option-
ally be divided by writing a one to DIVEN and the division factor to DIV, resulting in the output
frequency:
The generic clock can be disabled by writing a zero to CEN or entering a sleep mode that dis-
ables the PB clocks. In either case, the generic clock will be switched off on the first falling edge
after the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still
read as one until the next falling edge occurs, and the clock is actually switched off. When writ-
ing a zero to CEN, the other bits in GCCTRL should not be changed until CEN reads as zero, to
avoid glitches on the generic clock.
When the clock is disabled, both the prescaler and output are reset.
When changing generic clock frequency by writing GCCTRL, the clock should be switched off by
the procedure above, before being re-enabled with the new clock source or division setting. This
prevents glitches during the transition.
In AT32UC3C, the generic clocks are allocated to different functions as shown in
Table 8-2.
Clock number
f
GCLK
0
1
2
= f
SRC
Generic clock generation
Generic clock allocation
/
Function
USB clock (48 MHz)
CANIF
AST
(2*(DIV+1))
Divider
DIV
DIVEN
0
1
Sleep Controller
Mask
CEN
Name
GCLK_USBC
GCLK_CANIF
GCLK_AST
Generic Clock
AT32UC3C
Table
8-2.
85
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